Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Overload reset is accepted while the overload contact is still open · case 01
Pressing reset with the heater element still tripped lets the motor restart on a live overload.
Overload reset is accepted while the overload contact is still open · case 02
Pressing reset with the heater element still tripped lets the motor restart on a live overload.
Overload reset is accepted while the overload contact is still open · case 03
Pressing reset with the heater element still tripped lets the motor restart on a live overload.
Overload reset is accepted while the overload contact is still open · case 04
Pressing reset with the heater element still tripped lets the motor restart on a live overload.
Overload reset is accepted while the overload contact is still open · case 05
Pressing reset with the heater element still tripped lets the motor restart on a live overload.
Overload trip resets itself when the contact recloses · case 01
The motor restarts on the next start press after the overload cools, without an operator reset.
Overload trip resets itself when the contact recloses · case 02
The motor restarts on the next start press after the overload cools, without an operator reset.
Overload trip resets itself when the contact recloses · case 03
The motor restarts on the next start press after the overload cools, without an operator reset.
Overload trip resets itself when the contact recloses · case 04
The motor restarts on the next start press after the overload cools, without an operator reset.
Overload trip resets itself when the contact recloses · case 05
The motor restarts on the next start press after the overload cools, without an operator reset.
Overload trip is forgotten across a power loss · case 01
Cycling control power clears a latched overload trip so the motor can restart without reset.
Overload trip is forgotten across a power loss · case 02
Cycling control power clears a latched overload trip so the motor can restart without reset.
Overload trip is forgotten across a power loss · case 03
Cycling control power clears a latched overload trip so the motor can restart without reset.
Overload trip is forgotten across a power loss · case 04
Cycling control power clears a latched overload trip so the motor can restart without reset.
Overload trip is forgotten across a power loss · case 05
Cycling control power clears a latched overload trip so the motor can restart without reset.
Motor restarts after power returns while start is still held · case 01
A jammed or held start button restarts the machine automatically when power is restored.
Motor restarts after power returns while start is still held · case 02
A jammed or held start button restarts the machine automatically when power is restored.
Motor restarts after power returns while start is still held · case 03
A jammed or held start button restarts the machine automatically when power is restored.
Motor restarts after power returns while start is still held · case 04
A jammed or held start button restarts the machine automatically when power is restored.
Motor restarts after power returns while start is still held · case 05
A jammed or held start button restarts the machine automatically when power is restored.
Motor starter drops out when the start button is released · case 01
The motor only runs while start is held, like a jog circuit.
Motor starter drops out when the start button is released · case 02
The motor only runs while start is held, like a jog circuit.
Motor starter drops out when the start button is released · case 03
The motor only runs while start is held, like a jog circuit.
Motor starter drops out when the start button is released · case 04
The motor only runs while start is held, like a jog circuit.
Motor starter drops out when the start button is released · case 05
The motor only runs while start is held, like a jog circuit.
Start button overrides stop and trip in the same scan · case 01
Holding start while pressing stop keeps the motor running.
Start button overrides stop and trip in the same scan · case 02
Holding start while pressing stop keeps the motor running.
Start button overrides stop and trip in the same scan · case 03
Holding start while pressing stop keeps the motor running.
Start button overrides stop and trip in the same scan · case 04
Holding start while pressing stop keeps the motor running.
Start button overrides stop and trip in the same scan · case 05
Holding start while pressing stop keeps the motor running.
Power cycle clears latched OTL bits · case 01
A latched mode or fault memory is lost after a controller power cycle.
Power cycle clears latched OTL bits · case 02
A latched mode or fault memory is lost after a controller power cycle.
Power cycle clears latched OTL bits · case 03
A latched mode or fault memory is lost after a controller power cycle.
Power cycle clears latched OTL bits · case 04
A latched mode or fault memory is lost after a controller power cycle.
Power cycle clears latched OTL bits · case 05
A latched mode or fault memory is lost after a controller power cycle.
First-scan bit is not re-armed after a power cycle · case 01
Initialization rungs conditioned on the first-scan bit run at initial power-up but not after later restarts.
First-scan bit is not re-armed after a power cycle · case 02
Initialization rungs conditioned on the first-scan bit run at initial power-up but not after later restarts.
First-scan bit is not re-armed after a power cycle · case 03
Initialization rungs conditioned on the first-scan bit run at initial power-up but not after later restarts.
First-scan bit is not re-armed after a power cycle · case 04
Initialization rungs conditioned on the first-scan bit run at initial power-up but not after later restarts.
First-scan bit is not re-armed after a power cycle · case 05
Initialization rungs conditioned on the first-scan bit run at initial power-up but not after later restarts.
OTL clears its bit when its rung is false · case 01
A latch behaves like an ordinary output coil and drops as soon as its condition goes away.
OTL clears its bit when its rung is false · case 02
A latch behaves like an ordinary output coil and drops as soon as its condition goes away.
OTL clears its bit when its rung is false · case 03
A latch behaves like an ordinary output coil and drops as soon as its condition goes away.
OTL clears its bit when its rung is false · case 04
A latch behaves like an ordinary output coil and drops as soon as its condition goes away.
OTL clears its bit when its rung is false · case 05
A latch behaves like an ordinary output coil and drops as soon as its condition goes away.
Latch and unlatch rungs are evaluated bottom-up · case 01
When latch and unlatch conditions are true together the opposite rung wins from what the program order dictates.
Latch and unlatch rungs are evaluated bottom-up · case 02
When latch and unlatch conditions are true together the opposite rung wins from what the program order dictates.
Latch and unlatch rungs are evaluated bottom-up · case 03
When latch and unlatch conditions are true together the opposite rung wins from what the program order dictates.
Latch and unlatch rungs are evaluated bottom-up · case 04
When latch and unlatch conditions are true together the opposite rung wins from what the program order dictates.
Latch and unlatch rungs are evaluated bottom-up · case 05
When latch and unlatch conditions are true together the opposite rung wins from what the program order dictates.
Non-retentive outputs survive a power cycle · case 01
An output coil that was on before the power loss is reported on after prescan, before its rung has been solved.
Non-retentive outputs survive a power cycle · case 02
An output coil that was on before the power loss is reported on after prescan, before its rung has been solved.
Non-retentive outputs survive a power cycle · case 03
An output coil that was on before the power loss is reported on after prescan, before its rung has been solved.
Non-retentive outputs survive a power cycle · case 04
An output coil that was on before the power loss is reported on after prescan, before its rung has been solved.
Non-retentive outputs survive a power cycle · case 05
An output coil that was on before the power loss is reported on after prescan, before its rung has been solved.
A trigger at the exact completion time is counted as a task overlap · case 01
Periodic tasks whose execution equals the period are skipped every other cycle and the overlap counter climbs.
A trigger at the exact completion time is counted as a task overlap · case 02
Periodic tasks whose execution equals the period are skipped every other cycle and the overlap counter climbs.
A trigger at the exact completion time is counted as a task overlap · case 03
Periodic tasks whose execution equals the period are skipped every other cycle and the overlap counter climbs.
A trigger at the exact completion time is counted as a task overlap · case 04
Periodic tasks whose execution equals the period are skipped every other cycle and the overlap counter climbs.
A trigger at the exact completion time is counted as a task overlap · case 05
Periodic tasks whose execution equals the period are skipped every other cycle and the overlap counter climbs.
Overlapped periodic triggers are queued behind the running execution · case 01
Start times drift off the period grid after an overrun because missed triggers run late.
Overlapped periodic triggers are queued behind the running execution · case 02
Start times drift off the period grid after an overrun because missed triggers run late.
Overlapped periodic triggers are queued behind the running execution · case 03
Start times drift off the period grid after an overrun because missed triggers run late.
Overlapped periodic triggers are queued behind the running execution · case 04
Start times drift off the period grid after an overrun because missed triggers run late.
Overlapped periodic triggers are queued behind the running execution · case 05
Start times drift off the period grid after an overrun because missed triggers run late.
Task watchdog faults on an execution exactly equal to its limit · case 01
A task that finishes precisely at the watchdog time causes a major fault.
Task watchdog faults on an execution exactly equal to its limit · case 02
A task that finishes precisely at the watchdog time causes a major fault.
Task watchdog faults on an execution exactly equal to its limit · case 03
A task that finishes precisely at the watchdog time causes a major fault.
Task watchdog faults on an execution exactly equal to its limit · case 04
A task that finishes precisely at the watchdog time causes a major fault.
Task watchdog faults on an execution exactly equal to its limit · case 05
A task that finishes precisely at the watchdog time causes a major fault.
Watchdog fault time is reported at the end of the overrunning execution · case 01
The major fault is logged later than it occurred, after the watchdog should already have stopped the task.
Watchdog fault time is reported at the end of the overrunning execution · case 02
The major fault is logged later than it occurred, after the watchdog should already have stopped the task.
Watchdog fault time is reported at the end of the overrunning execution · case 03
The major fault is logged later than it occurred, after the watchdog should already have stopped the task.
Watchdog fault time is reported at the end of the overrunning execution · case 04
The major fault is logged later than it occurred, after the watchdog should already have stopped the task.
Watchdog fault time is reported at the end of the overrunning execution · case 05
The major fault is logged later than it occurred, after the watchdog should already have stopped the task.
Periodic trigger is scheduled relative to the previous start · case 01
After a skipped trigger the task phase shifts permanently instead of returning to the fixed period grid.
Periodic trigger is scheduled relative to the previous start · case 02
After a skipped trigger the task phase shifts permanently instead of returning to the fixed period grid.
Periodic trigger is scheduled relative to the previous start · case 03
After a skipped trigger the task phase shifts permanently instead of returning to the fixed period grid.
Periodic trigger is scheduled relative to the previous start · case 04
After a skipped trigger the task phase shifts permanently instead of returning to the fixed period grid.
Periodic trigger is scheduled relative to the previous start · case 05
After a skipped trigger the task phase shifts permanently instead of returning to the fixed period grid.
Sequencer wraps to the home element instead of step 1 · case 01
After the last step the machine outputs the home pattern and needs an extra advance before step 1.
Sequencer wraps to the home element instead of step 1 · case 02
After the last step the machine outputs the home pattern and needs an extra advance before step 1.
Sequencer wraps to the home element instead of step 1 · case 03
After the last step the machine outputs the home pattern and needs an extra advance before step 1.
Sequencer wraps to the home element instead of step 1 · case 04
After the last step the machine outputs the home pattern and needs an extra advance before step 1.
Sequencer wraps to the home element instead of step 1 · case 05
After the last step the machine outputs the home pattern and needs an extra advance before step 1.
Sequencer wraps before reaching its last step · case 01
The final element of the sequencer file is never output.
Sequencer wraps before reaching its last step · case 02
The final element of the sequencer file is never output.
Sequencer wraps before reaching its last step · case 03
The final element of the sequencer file is never output.
Sequencer wraps before reaching its last step · case 04
The final element of the sequencer file is never output.
Sequencer wraps before reaching its last step · case 05
The final element of the sequencer file is never output.
Sequencer write clobbers destination bits outside the mask · case 01
Outputs that other rungs control on the same word are cleared on every sequencer step.
Sequencer write clobbers destination bits outside the mask · case 02
Outputs that other rungs control on the same word are cleared on every sequencer step.
Sequencer write clobbers destination bits outside the mask · case 03
Outputs that other rungs control on the same word are cleared on every sequencer step.
Sequencer write clobbers destination bits outside the mask · case 04
Outputs that other rungs control on the same word are cleared on every sequencer step.
Sequencer write clobbers destination bits outside the mask · case 05
Outputs that other rungs control on the same word are cleared on every sequencer step.
Sequencer advances every scan while enable is held · case 01
Holding the step input races through the whole sequence.
Sequencer advances every scan while enable is held · case 02
Holding the step input races through the whole sequence.
Sequencer advances every scan while enable is held · case 03
Holding the step input races through the whole sequence.
Sequencer advances every scan while enable is held · case 04
Holding the step input races through the whole sequence.
Sequencer advances every scan while enable is held · case 05
Holding the step input races through the whole sequence.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗