Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
RES rung is applied before the RTO rung in the same scan · case 01
On a reset scan with the timer enabled, ACC ends the scan non-zero instead of cleared.
RES rung is applied before the RTO rung in the same scan · case 02
On a reset scan with the timer enabled, ACC ends the scan non-zero instead of cleared.
RES rung is applied before the RTO rung in the same scan · case 03
On a reset scan with the timer enabled, ACC ends the scan non-zero instead of cleared.
RES rung is applied before the RTO rung in the same scan · case 04
On a reset scan with the timer enabled, ACC ends the scan non-zero instead of cleared.
RES rung is applied before the RTO rung in the same scan · case 05
On a reset scan with the timer enabled, ACC ends the scan non-zero instead of cleared.
RES clears the RTO accumulator but leaves DN latched · case 01
After a reset the done bit stays on while ACC reads zero.
RES clears the RTO accumulator but leaves DN latched · case 02
After a reset the done bit stays on while ACC reads zero.
RES clears the RTO accumulator but leaves DN latched · case 03
After a reset the done bit stays on while ACC reads zero.
RES clears the RTO accumulator but leaves DN latched · case 04
After a reset the done bit stays on while ACC reads zero.
RES clears the RTO accumulator but leaves DN latched · case 05
After a reset the done bit stays on while ACC reads zero.
RES also clears the RTO enable edge memory · case 01
After a reset issued while the timer stays enabled, the next scan is not credited and completion is late.
RES also clears the RTO enable edge memory · case 02
After a reset issued while the timer stays enabled, the next scan is not credited and completion is late.
RES also clears the RTO enable edge memory · case 03
After a reset issued while the timer stays enabled, the next scan is not credited and completion is late.
RES also clears the RTO enable edge memory · case 04
After a reset issued while the timer stays enabled, the next scan is not credited and completion is late.
RES also clears the RTO enable edge memory · case 05
After a reset issued while the timer stays enabled, the next scan is not credited and completion is late.
CTU counts every scan the input is held · case 01
Holding the count input for several scans adds several counts instead of one.
CTU counts every scan the input is held · case 02
Holding the count input for several scans adds several counts instead of one.
CTU counts every scan the input is held · case 03
Holding the count input for several scans adds several counts instead of one.
CTU counts every scan the input is held · case 04
Holding the count input for several scans adds several counts instead of one.
CTU counts every scan the input is held · case 05
Holding the count input for several scans adds several counts instead of one.
CTU edge memory is refreshed only when a count occurs · case 01
After the first count, further pulses on the up input are ignored until the counter is reset.
CTU edge memory is refreshed only when a count occurs · case 02
After the first count, further pulses on the up input are ignored until the counter is reset.
CTU edge memory is refreshed only when a count occurs · case 03
After the first count, further pulses on the up input are ignored until the counter is reset.
CTU edge memory is refreshed only when a count occurs · case 04
After the first count, further pulses on the up input are ignored until the counter is reset.
CTU edge memory is refreshed only when a count occurs · case 05
After the first count, further pulses on the up input are ignored until the counter is reset.
CTU saturates instead of wrapping at 32767 · case 01
Counting past the 16-bit limit leaves ACC at 32767 although OV is set.
CTU saturates instead of wrapping at 32767 · case 02
Counting past the 16-bit limit leaves ACC at 32767 although OV is set.
CTU saturates instead of wrapping at 32767 · case 03
Counting past the 16-bit limit leaves ACC at 32767 although OV is set.
CTU saturates instead of wrapping at 32767 · case 04
Counting past the 16-bit limit leaves ACC at 32767 although OV is set.
CTU saturates instead of wrapping at 32767 · case 05
Counting past the 16-bit limit leaves ACC at 32767 although OV is set.
CTU overflow bit clears on the next up count · case 01
OV disappears after one more count even though no reset occurred.
CTU overflow bit clears on the next up count · case 02
OV disappears after one more count even though no reset occurred.
CTU overflow bit clears on the next up count · case 03
OV disappears after one more count even though no reset occurred.
CTU overflow bit clears on the next up count · case 04
OV disappears after one more count even though no reset occurred.
CTU overflow bit clears on the next up count · case 05
OV disappears after one more count even though no reset occurred.
Counter reset leaves overflow and underflow latched · case 01
After RES the accumulator reads zero but OV or UN is still set.
Counter reset leaves overflow and underflow latched · case 02
After RES the accumulator reads zero but OV or UN is still set.
Counter reset leaves overflow and underflow latched · case 03
After RES the accumulator reads zero but OV or UN is still set.
Counter reset leaves overflow and underflow latched · case 04
After RES the accumulator reads zero but OV or UN is still set.
Counter reset leaves overflow and underflow latched · case 05
After RES the accumulator reads zero but OV or UN is still set.
Counter done bit only matches the exact preset · case 01
DN turns off as soon as the count passes the preset.
Counter done bit only matches the exact preset · case 02
DN turns off as soon as the count passes the preset.
Counter done bit only matches the exact preset · case 03
DN turns off as soon as the count passes the preset.
Counter done bit only matches the exact preset · case 04
DN turns off as soon as the count passes the preset.
Counter done bit only matches the exact preset · case 05
DN turns off as soon as the count passes the preset.
Down count is skipped when an up count happens in the same scan · case 01
Coincident CU and CD edges net +1 instead of cancelling.
Down count is skipped when an up count happens in the same scan · case 02
Coincident CU and CD edges net +1 instead of cancelling.
Down count is skipped when an up count happens in the same scan · case 03
Coincident CU and CD edges net +1 instead of cancelling.
Down count is skipped when an up count happens in the same scan · case 04
Coincident CU and CD edges net +1 instead of cancelling.
Down count is skipped when an up count happens in the same scan · case 05
Coincident CU and CD edges net +1 instead of cancelling.
Program scan reads live inputs instead of the frozen input image · case 01
Two rungs examining the same input disagree within one scan when the field signal changes mid-scan.
Program scan reads live inputs instead of the frozen input image · case 02
Two rungs examining the same input disagree within one scan when the field signal changes mid-scan.
Program scan reads live inputs instead of the frozen input image · case 03
Two rungs examining the same input disagree within one scan when the field signal changes mid-scan.
Program scan reads live inputs instead of the frozen input image · case 04
Two rungs examining the same input disagree within one scan when the field signal changes mid-scan.
Program scan reads live inputs instead of the frozen input image · case 05
Two rungs examining the same input disagree within one scan when the field signal changes mid-scan.
Later rungs read coil values from the previous scan · case 01
An internal bit set by rung 1 only affects rung 2 one scan later, adding a scan of delay.
Later rungs read coil values from the previous scan · case 02
An internal bit set by rung 1 only affects rung 2 one scan later, adding a scan of delay.
Later rungs read coil values from the previous scan · case 03
An internal bit set by rung 1 only affects rung 2 one scan later, adding a scan of delay.
Later rungs read coil values from the previous scan · case 04
An internal bit set by rung 1 only affects rung 2 one scan later, adding a scan of delay.
Later rungs read coil values from the previous scan · case 05
An internal bit set by rung 1 only affects rung 2 one scan later, adding a scan of delay.
XIO on a never-written tag evaluates false · case 01
A rung built on an examine-if-open contact stays off until the referenced bit has been written once.
XIO on a never-written tag evaluates false · case 02
A rung built on an examine-if-open contact stays off until the referenced bit has been written once.
XIO on a never-written tag evaluates false · case 03
A rung built on an examine-if-open contact stays off until the referenced bit has been written once.
XIO on a never-written tag evaluates false · case 04
A rung built on an examine-if-open contact stays off until the referenced bit has been written once.
XIO on a never-written tag evaluates false · case 05
A rung built on an examine-if-open contact stays off until the referenced bit has been written once.
Parallel rung branches are combined in series · case 01
A rung with two parallel paths requires both paths to be true.
Parallel rung branches are combined in series · case 02
A rung with two parallel paths requires both paths to be true.
Parallel rung branches are combined in series · case 03
A rung with two parallel paths requires both paths to be true.
Parallel rung branches are combined in series · case 04
A rung with two parallel paths requires both paths to be true.
Parallel rung branches are combined in series · case 05
A rung with two parallel paths requires both paths to be true.
Duplicate OTE coils are ORed within a scan · case 01
An output driven by two rungs stays on when the last rung writing it is false.
Duplicate OTE coils are ORed within a scan · case 02
An output driven by two rungs stays on when the last rung writing it is false.
Duplicate OTE coils are ORed within a scan · case 03
An output driven by two rungs stays on when the last rung writing it is false.
Duplicate OTE coils are ORed within a scan · case 04
An output driven by two rungs stays on when the last rung writing it is false.
Duplicate OTE coils are ORed within a scan · case 05
An output driven by two rungs stays on when the last rung writing it is false.
OSR fires on the first scan when its input is already on at power-up · case 01
A start sequence is triggered by a restart because an input that was already held on is seen as a new rising edge.
OSR fires on the first scan when its input is already on at power-up · case 02
A start sequence is triggered by a restart because an input that was already held on is seen as a new rising edge.
OSR fires on the first scan when its input is already on at power-up · case 03
A start sequence is triggered by a restart because an input that was already held on is seen as a new rising edge.
OSR fires on the first scan when its input is already on at power-up · case 04
A start sequence is triggered by a restart because an input that was already held on is seen as a new rising edge.
OSR fires on the first scan when its input is already on at power-up · case 05
A start sequence is triggered by a restart because an input that was already held on is seen as a new rising edge.
OSF pulses on every scan the input is off · case 01
The falling one-shot output stays on continuously instead of for one scan.
OSF pulses on every scan the input is off · case 02
The falling one-shot output stays on continuously instead of for one scan.
OSF pulses on every scan the input is off · case 03
The falling one-shot output stays on continuously instead of for one scan.
OSF pulses on every scan the input is off · case 04
The falling one-shot output stays on continuously instead of for one scan.
OSF pulses on every scan the input is off · case 05
The falling one-shot output stays on continuously instead of for one scan.
One-shot storage bit only updates when a pulse is produced · case 01
After one pulse the instruction never fires again because its storage bit is never refreshed to the input.
One-shot storage bit only updates when a pulse is produced · case 02
After one pulse the instruction never fires again because its storage bit is never refreshed to the input.
One-shot storage bit only updates when a pulse is produced · case 03
After one pulse the instruction never fires again because its storage bit is never refreshed to the input.
One-shot storage bit only updates when a pulse is produced · case 04
After one pulse the instruction never fires again because its storage bit is never refreshed to the input.
One-shot storage bit only updates when a pulse is produced · case 05
After one pulse the instruction never fires again because its storage bit is never refreshed to the input.
One-shots sharing a storage bit are simulated with private storage · case 01
The simulated program misses the interaction where one instruction consumes the edge for another sharing the same bit.
One-shots sharing a storage bit are simulated with private storage · case 02
The simulated program misses the interaction where one instruction consumes the edge for another sharing the same bit.
One-shots sharing a storage bit are simulated with private storage · case 03
The simulated program misses the interaction where one instruction consumes the edge for another sharing the same bit.
One-shots sharing a storage bit are simulated with private storage · case 04
The simulated program misses the interaction where one instruction consumes the edge for another sharing the same bit.
One-shots sharing a storage bit are simulated with private storage · case 05
The simulated program misses the interaction where one instruction consumes the edge for another sharing the same bit.
Normally-closed stop input is examined as if normally open · case 01
The motor only runs while the stop button is held and stops as soon as it is released.
Normally-closed stop input is examined as if normally open · case 02
The motor only runs while the stop button is held and stops as soon as it is released.
Normally-closed stop input is examined as if normally open · case 03
The motor only runs while the stop button is held and stops as soon as it is released.
Normally-closed stop input is examined as if normally open · case 04
The motor only runs while the stop button is held and stops as soon as it is released.
Normally-closed stop input is examined as if normally open · case 05
The motor only runs while the stop button is held and stops as soon as it is released.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗