FAILURE MAP

Understand the failure.
Verify the repair.

Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.

Explore the cases ↓How results are verified ↗
100840Executable case variants
20168Distinct failure mechanisms
302520Executed implementations
20168Open-access cases

WHAT THE ARCHIVE CONTAINS

100840 executable cases. 20168 are open.

Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.

The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗

A RECORD OF WHAT WENT WRONG

Browse the archive / 100840

Python · Standard library
REFERENCEFAILURE MECHANISMDOMAINACCESS
FA-91801

Q15 FIR pushes new samples onto the wrong end of the delay line · case 01

The impulse response comes out reversed for asymmetric taps.

Digital signal filters● Open access↗
FA-91802

Q15 FIR pushes new samples onto the wrong end of the delay line · case 02

The impulse response comes out reversed for asymmetric taps.

Digital signal filters◈ Members↗
FA-91803

Q15 FIR pushes new samples onto the wrong end of the delay line · case 03

The impulse response comes out reversed for asymmetric taps.

Digital signal filters◈ Members↗
FA-91804

Q15 FIR pushes new samples onto the wrong end of the delay line · case 04

The impulse response comes out reversed for asymmetric taps.

Digital signal filters◈ Members↗
FA-91805

Q15 FIR pushes new samples onto the wrong end of the delay line · case 05

The impulse response comes out reversed for asymmetric taps.

Digital signal filters◈ Members↗
FA-91806

Notch design places the zeros at half the tone frequency · case 01

A 50 Hz notch at 1 kHz sampling attenuates 25 Hz instead.

Digital signal filters● Open access↗
FA-91807

Notch design places the zeros at half the tone frequency · case 02

A 50 Hz notch at 1 kHz sampling attenuates 25 Hz instead.

Digital signal filters◈ Members↗
FA-91808

Notch design places the zeros at half the tone frequency · case 03

A 50 Hz notch at 1 kHz sampling attenuates 25 Hz instead.

Digital signal filters◈ Members↗
FA-91809

Notch design places the zeros at half the tone frequency · case 04

A 50 Hz notch at 1 kHz sampling attenuates 25 Hz instead.

Digital signal filters◈ Members↗
FA-91810

Notch design places the zeros at half the tone frequency · case 05

A 50 Hz notch at 1 kHz sampling attenuates 25 Hz instead.

Digital signal filters◈ Members↗
FA-91811

Notch design uses r instead of r^2 for a2 · case 01

The poles do not sit at radius r; the notch is far wider than specified.

Digital signal filters● Open access↗
FA-91812

Notch design uses r instead of r^2 for a2 · case 02

The poles do not sit at radius r; the notch is far wider than specified.

Digital signal filters◈ Members↗
FA-91813

Notch design uses r instead of r^2 for a2 · case 03

The poles do not sit at radius r; the notch is far wider than specified.

Digital signal filters◈ Members↗
FA-91814

Notch design uses r instead of r^2 for a2 · case 04

The poles do not sit at radius r; the notch is far wider than specified.

Digital signal filters◈ Members↗
FA-91815

Notch design uses r instead of r^2 for a2 · case 05

The poles do not sit at radius r; the notch is far wider than specified.

Digital signal filters◈ Members↗
FA-91816

Notch design places the zeros at pi - w0 · case 01

The notch appears at fs/2 - f0.

Digital signal filters● Open access↗
FA-91817

Notch design places the zeros at pi - w0 · case 02

The notch appears at fs/2 - f0.

Digital signal filters◈ Members↗
FA-91818

Notch design places the zeros at pi - w0 · case 03

The notch appears at fs/2 - f0.

Digital signal filters◈ Members↗
FA-91819

Notch design places the zeros at pi - w0 · case 04

The notch appears at fs/2 - f0.

Digital signal filters◈ Members↗
FA-91820

Notch design places the zeros at pi - w0 · case 05

The notch appears at fs/2 - f0.

Digital signal filters◈ Members↗
FA-91821

Notch design inverts the DC gain correction · case 01

The passband gain is squared away from unity instead of corrected.

Digital signal filters● Open access↗
FA-91822

Notch design inverts the DC gain correction · case 02

The passband gain is squared away from unity instead of corrected.

Digital signal filters◈ Members↗
FA-91823

Notch design inverts the DC gain correction · case 03

The passband gain is squared away from unity instead of corrected.

Digital signal filters◈ Members↗
FA-91824

Notch design inverts the DC gain correction · case 04

The passband gain is squared away from unity instead of corrected.

Digital signal filters◈ Members↗
FA-91825

Notch design inverts the DC gain correction · case 05

The passband gain is squared away from unity instead of corrected.

Digital signal filters◈ Members↗
FA-91826

Allpass adds the feedback term · case 01

The magnitude response is no longer flat; the section boosts low frequencies.

Digital signal filters● Open access↗
FA-91827

Allpass adds the feedback term · case 02

The magnitude response is no longer flat; the section boosts low frequencies.

Digital signal filters◈ Members↗
FA-91828

Allpass adds the feedback term · case 03

The magnitude response is no longer flat; the section boosts low frequencies.

Digital signal filters◈ Members↗
FA-91829

Allpass adds the feedback term · case 04

The magnitude response is no longer flat; the section boosts low frequencies.

Digital signal filters◈ Members↗
FA-91830

Allpass adds the feedback term · case 05

The magnitude response is no longer flat; the section boosts low frequencies.

Digital signal filters◈ Members↗
FA-91831

Allpass passes the input without the a coefficient · case 01

The section is not allpass; its DC gain differs from 1.

Digital signal filters● Open access↗
FA-91832

Allpass passes the input without the a coefficient · case 02

The section is not allpass; its DC gain differs from 1.

Digital signal filters◈ Members↗
FA-91833

Allpass passes the input without the a coefficient · case 03

The section is not allpass; its DC gain differs from 1.

Digital signal filters◈ Members↗
FA-91834

Allpass passes the input without the a coefficient · case 04

The section is not allpass; its DC gain differs from 1.

Digital signal filters◈ Members↗
FA-91835

Allpass passes the input without the a coefficient · case 05

The section is not allpass; its DC gain differs from 1.

Digital signal filters◈ Members↗
FA-91836

Allpass swaps the input and output delay slots · case 01

The impulse response differs from the allpass kernel after the first sample.

Digital signal filters● Open access↗
FA-91837

Allpass swaps the input and output delay slots · case 02

The impulse response differs from the allpass kernel after the first sample.

Digital signal filters◈ Members↗
FA-91838

Allpass swaps the input and output delay slots · case 03

The impulse response differs from the allpass kernel after the first sample.

Digital signal filters◈ Members↗
FA-91839

Allpass swaps the input and output delay slots · case 04

The impulse response differs from the allpass kernel after the first sample.

Digital signal filters◈ Members↗
FA-91840

Allpass swaps the input and output delay slots · case 05

The impulse response differs from the allpass kernel after the first sample.

Digital signal filters◈ Members↗
FA-91841

TON credits the interval before the rung went true · case 01

The on-delay finishes one scan early because the scan that energized the rung already contributes elapsed time.

PLC ladder logic scan cycles● Open access↗
FA-91842

TON credits the interval before the rung went true · case 02

The on-delay finishes one scan early because the scan that energized the rung already contributes elapsed time.

PLC ladder logic scan cycles◈ Members↗
FA-91843

TON credits the interval before the rung went true · case 03

The on-delay finishes one scan early because the scan that energized the rung already contributes elapsed time.

PLC ladder logic scan cycles◈ Members↗
FA-91844

TON credits the interval before the rung went true · case 04

The on-delay finishes one scan early because the scan that energized the rung already contributes elapsed time.

PLC ladder logic scan cycles◈ Members↗
FA-91845

TON credits the interval before the rung went true · case 05

The on-delay finishes one scan early because the scan that energized the rung already contributes elapsed time.

PLC ladder logic scan cycles◈ Members↗
FA-91846

TON accumulator runs past its preset · case 01

After the delay completes the ACC value keeps growing on every true scan instead of holding at PRE.

PLC ladder logic scan cycles● Open access↗
FA-91847

TON accumulator runs past its preset · case 02

After the delay completes the ACC value keeps growing on every true scan instead of holding at PRE.

PLC ladder logic scan cycles◈ Members↗
FA-91848

TON accumulator runs past its preset · case 03

After the delay completes the ACC value keeps growing on every true scan instead of holding at PRE.

PLC ladder logic scan cycles◈ Members↗
FA-91849

TON accumulator runs past its preset · case 04

After the delay completes the ACC value keeps growing on every true scan instead of holding at PRE.

PLC ladder logic scan cycles◈ Members↗
FA-91850

TON accumulator runs past its preset · case 05

After the delay completes the ACC value keeps growing on every true scan instead of holding at PRE.

PLC ladder logic scan cycles◈ Members↗
FA-91851

TON behaves retentively when its rung drops · case 01

A second energization completes too soon because time accumulated before an interruption is kept.

PLC ladder logic scan cycles● Open access↗
FA-91852

TON behaves retentively when its rung drops · case 02

A second energization completes too soon because time accumulated before an interruption is kept.

PLC ladder logic scan cycles◈ Members↗
FA-91853

TON behaves retentively when its rung drops · case 03

A second energization completes too soon because time accumulated before an interruption is kept.

PLC ladder logic scan cycles◈ Members↗
FA-91854

TON behaves retentively when its rung drops · case 04

A second energization completes too soon because time accumulated before an interruption is kept.

PLC ladder logic scan cycles◈ Members↗
FA-91855

TON behaves retentively when its rung drops · case 05

A second energization completes too soon because time accumulated before an interruption is kept.

PLC ladder logic scan cycles◈ Members↗
FA-91856

TON done bit waits for ACC to exceed a clamped preset · case 01

A running timer never reports done even though ACC equals PRE.

PLC ladder logic scan cycles● Open access↗
FA-91857

TON done bit waits for ACC to exceed a clamped preset · case 02

A running timer never reports done even though ACC equals PRE.

PLC ladder logic scan cycles◈ Members↗
FA-91858

TON done bit waits for ACC to exceed a clamped preset · case 03

A running timer never reports done even though ACC equals PRE.

PLC ladder logic scan cycles◈ Members↗
FA-91859

TON done bit waits for ACC to exceed a clamped preset · case 04

A running timer never reports done even though ACC equals PRE.

PLC ladder logic scan cycles◈ Members↗
FA-91860

TON done bit waits for ACC to exceed a clamped preset · case 05

A running timer never reports done even though ACC equals PRE.

PLC ladder logic scan cycles◈ Members↗
FA-91861

TON timing bit stays on after the delay completes · case 01

TT and DN are both true on the same scan once the timer has finished.

PLC ladder logic scan cycles● Open access↗
FA-91862

TON timing bit stays on after the delay completes · case 02

TT and DN are both true on the same scan once the timer has finished.

PLC ladder logic scan cycles◈ Members↗
FA-91863

TON timing bit stays on after the delay completes · case 03

TT and DN are both true on the same scan once the timer has finished.

PLC ladder logic scan cycles◈ Members↗
FA-91864

TON timing bit stays on after the delay completes · case 04

TT and DN are both true on the same scan once the timer has finished.

PLC ladder logic scan cycles◈ Members↗
FA-91865

TON timing bit stays on after the delay completes · case 05

TT and DN are both true on the same scan once the timer has finished.

PLC ladder logic scan cycles◈ Members↗
FA-91866

Zero-preset TON reports done with a false rung · case 01

A timer with a zero preset shows DN set on scans where its rung is false.

PLC ladder logic scan cycles● Open access↗
FA-91867

Zero-preset TON reports done with a false rung · case 02

A timer with a zero preset shows DN set on scans where its rung is false.

PLC ladder logic scan cycles◈ Members↗
FA-91868

Zero-preset TON reports done with a false rung · case 03

A timer with a zero preset shows DN set on scans where its rung is false.

PLC ladder logic scan cycles◈ Members↗
FA-91869

Zero-preset TON reports done with a false rung · case 04

A timer with a zero preset shows DN set on scans where its rung is false.

PLC ladder logic scan cycles◈ Members↗
FA-91870

Zero-preset TON reports done with a false rung · case 05

A timer with a zero preset shows DN set on scans where its rung is false.

PLC ladder logic scan cycles◈ Members↗
FA-91871

TOF output energizes at power-up with a false rung · case 01

After a restart the off-delay output is on for a full preset even though its rung was never true.

PLC ladder logic scan cycles● Open access↗
FA-91872

TOF output energizes at power-up with a false rung · case 02

After a restart the off-delay output is on for a full preset even though its rung was never true.

PLC ladder logic scan cycles◈ Members↗
FA-91873

TOF output energizes at power-up with a false rung · case 03

After a restart the off-delay output is on for a full preset even though its rung was never true.

PLC ladder logic scan cycles◈ Members↗
FA-91874

TOF output energizes at power-up with a false rung · case 04

After a restart the off-delay output is on for a full preset even though its rung was never true.

PLC ladder logic scan cycles◈ Members↗
FA-91875

TOF output energizes at power-up with a false rung · case 05

After a restart the off-delay output is on for a full preset even though its rung was never true.

PLC ladder logic scan cycles◈ Members↗
FA-91876

TOF keeps stale delay time when its rung returns · case 01

An off-delay that is re-energized mid-delay then expires early on the next drop.

PLC ladder logic scan cycles● Open access↗
FA-91877

TOF keeps stale delay time when its rung returns · case 02

An off-delay that is re-energized mid-delay then expires early on the next drop.

PLC ladder logic scan cycles◈ Members↗
FA-91878

TOF keeps stale delay time when its rung returns · case 03

An off-delay that is re-energized mid-delay then expires early on the next drop.

PLC ladder logic scan cycles◈ Members↗
FA-91879

TOF keeps stale delay time when its rung returns · case 04

An off-delay that is re-energized mid-delay then expires early on the next drop.

PLC ladder logic scan cycles◈ Members↗
FA-91880

TOF keeps stale delay time when its rung returns · case 05

An off-delay that is re-energized mid-delay then expires early on the next drop.

PLC ladder logic scan cycles◈ Members↗
FA-91881

TOF credits the scan on which the rung dropped · case 01

The output turns off one scan early because the de-energizing scan already contributes time.

PLC ladder logic scan cycles● Open access↗
FA-91882

TOF credits the scan on which the rung dropped · case 02

The output turns off one scan early because the de-energizing scan already contributes time.

PLC ladder logic scan cycles◈ Members↗
FA-91883

TOF credits the scan on which the rung dropped · case 03

The output turns off one scan early because the de-energizing scan already contributes time.

PLC ladder logic scan cycles◈ Members↗
FA-91884

TOF credits the scan on which the rung dropped · case 04

The output turns off one scan early because the de-energizing scan already contributes time.

PLC ladder logic scan cycles◈ Members↗
FA-91885

TOF credits the scan on which the rung dropped · case 05

The output turns off one scan early because the de-energizing scan already contributes time.

PLC ladder logic scan cycles◈ Members↗
FA-91886

TOF never expires once ACC is clamped · case 01

The off-delay output stays on forever after the rung drops.

PLC ladder logic scan cycles● Open access↗
FA-91887

TOF never expires once ACC is clamped · case 02

The off-delay output stays on forever after the rung drops.

PLC ladder logic scan cycles◈ Members↗
FA-91888

TOF never expires once ACC is clamped · case 03

The off-delay output stays on forever after the rung drops.

PLC ladder logic scan cycles◈ Members↗
FA-91889

TOF never expires once ACC is clamped · case 04

The off-delay output stays on forever after the rung drops.

PLC ladder logic scan cycles◈ Members↗
FA-91890

TOF never expires once ACC is clamped · case 05

The off-delay output stays on forever after the rung drops.

PLC ladder logic scan cycles◈ Members↗
FA-91891

TOF timing bit reports an expired timer as timing · case 01

TT is true on false-rung scans after the off-delay has already finished, and at power-up.

PLC ladder logic scan cycles● Open access↗
FA-91892

TOF timing bit reports an expired timer as timing · case 02

TT is true on false-rung scans after the off-delay has already finished, and at power-up.

PLC ladder logic scan cycles◈ Members↗
FA-91893

TOF timing bit reports an expired timer as timing · case 03

TT is true on false-rung scans after the off-delay has already finished, and at power-up.

PLC ladder logic scan cycles◈ Members↗
FA-91894

TOF timing bit reports an expired timer as timing · case 04

TT is true on false-rung scans after the off-delay has already finished, and at power-up.

PLC ladder logic scan cycles◈ Members↗
FA-91895

TOF timing bit reports an expired timer as timing · case 05

TT is true on false-rung scans after the off-delay has already finished, and at power-up.

PLC ladder logic scan cycles◈ Members↗
FA-91896

RTO discards accumulated time when its rung goes false · case 01

A retentive timer loses its partial accumulation across a stop and restarts from zero.

PLC ladder logic scan cycles● Open access↗
FA-91897

RTO discards accumulated time when its rung goes false · case 02

A retentive timer loses its partial accumulation across a stop and restarts from zero.

PLC ladder logic scan cycles◈ Members↗
FA-91898

RTO discards accumulated time when its rung goes false · case 03

A retentive timer loses its partial accumulation across a stop and restarts from zero.

PLC ladder logic scan cycles◈ Members↗
FA-91899

RTO discards accumulated time when its rung goes false · case 04

A retentive timer loses its partial accumulation across a stop and restarts from zero.

PLC ladder logic scan cycles◈ Members↗
FA-91900

RTO discards accumulated time when its rung goes false · case 05

A retentive timer loses its partial accumulation across a stop and restarts from zero.

PLC ladder logic scan cycles◈ Members↗

INSPECTABLE BY DESIGN

Every result has a runnable source.

Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.

Read the methodology ↗