FA-91925 / PLC ladder logic scan cycles / Member archive

CTU edge memory is refreshed only when a count occurs · case 05

After the first count, further pulses on the up input are ignored until the counter is reset.

Member previewVariant 5 · 3 implementations · 8 checks per implementation

Case contract

Up/down counter pair sharing one 16-bit signed accumulator, evaluated per scan; scans is a list of [cu, cd, res]. CU counts on its rising edge and CD on its own rising edge (both in one scan cancel). Incrementing 32767 wraps to -32768 and latches OV; decrementing -32768 wraps to 32767 and latches UN. A later RES rung clears ACC, OV and UN but not the edge memories. DN is ACC >= preset. Return [ACC, DN, OV, UN] per scan.

Why this case matters

Ladder programs are executed as repeated scans; each defect here changes what a rung, timer, counter or data-table instruction reports on a particular scan, which is how commissioning and field faults are actually observed.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
regression: scenario 2	`[[32764, false, false, false], [32764, false, false, false], [32765, false, false, false], [32765, false, false, false], [32765, false, false, false], [32765, false, false, false], [0, false, false, false], [0, false, false, false], [-1, false, false, false], [-1, false, false, false], [-1, false, false, false], [-2, false, false, false]]`	`[[32764, false, false, false], [32764, false, false, false], [32765, false, false, false], [32765, false, false, false], [32766, false, false, false], [32766, false, false, false], [0, false, false, false], [0, false, false, false], [-1, false, false, false], [-1, false, false, false], [0, false, false, false], [-1, false, false, false]]`	Failed

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