Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Sequencer reset writes the home word to the destination · case 01
Resetting the sequencer changes the machine outputs instead of only rewinding the position.
Sequencer reset writes the home word to the destination · case 02
Resetting the sequencer changes the machine outputs instead of only rewinding the position.
Sequencer reset writes the home word to the destination · case 03
Resetting the sequencer changes the machine outputs instead of only rewinding the position.
Sequencer reset writes the home word to the destination · case 04
Resetting the sequencer changes the machine outputs instead of only rewinding the position.
Sequencer reset writes the home word to the destination · case 05
Resetting the sequencer changes the machine outputs instead of only rewinding the position.
Sequencer advances and writes on a scan that is also resetting · case 01
A reset coinciding with a step pulse outputs the next step pattern while the position reads 0.
Sequencer advances and writes on a scan that is also resetting · case 02
A reset coinciding with a step pulse outputs the next step pattern while the position reads 0.
Sequencer advances and writes on a scan that is also resetting · case 03
A reset coinciding with a step pulse outputs the next step pattern while the position reads 0.
Sequencer advances and writes on a scan that is also resetting · case 04
A reset coinciding with a step pulse outputs the next step pattern while the position reads 0.
Sequencer advances and writes on a scan that is also resetting · case 05
A reset coinciding with a step pulse outputs the next step pattern while the position reads 0.
Shift register unload bit is read after the shift · case 01
The reject gate acts on the part that is still one position upstream.
Shift register unload bit is read after the shift · case 02
The reject gate acts on the part that is still one position upstream.
Shift register unload bit is read after the shift · case 03
The reject gate acts on the part that is still one position upstream.
Shift register unload bit is read after the shift · case 04
The reject gate acts on the part that is still one position upstream.
Shift register unload bit is read after the shift · case 05
The reject gate acts on the part that is still one position upstream.
Shift register moves tracking bits toward the load end · case 01
Part-present bits travel backwards along the conveyor model.
Shift register moves tracking bits toward the load end · case 02
Part-present bits travel backwards along the conveyor model.
Shift register moves tracking bits toward the load end · case 03
Part-present bits travel backwards along the conveyor model.
Shift register moves tracking bits toward the load end · case 04
Part-present bits travel backwards along the conveyor model.
Shift register moves tracking bits toward the load end · case 05
Part-present bits travel backwards along the conveyor model.
Shift register shifts every scan while the encoder input is high · case 01
Tracking runs ahead of the conveyor when the encoder pulse spans several scans.
Shift register shifts every scan while the encoder input is high · case 02
Tracking runs ahead of the conveyor when the encoder pulse spans several scans.
Shift register shifts every scan while the encoder input is high · case 03
Tracking runs ahead of the conveyor when the encoder pulse spans several scans.
Shift register shifts every scan while the encoder input is high · case 04
Tracking runs ahead of the conveyor when the encoder pulse spans several scans.
Shift register shifts every scan while the encoder input is high · case 05
Tracking runs ahead of the conveyor when the encoder pulse spans several scans.
Shift register loads the sensor value from the previous scan · case 01
A part that arrives on the same scan as the encoder edge is not tracked.
Shift register loads the sensor value from the previous scan · case 02
A part that arrives on the same scan as the encoder edge is not tracked.
Shift register loads the sensor value from the previous scan · case 03
A part that arrives on the same scan as the encoder edge is not tracked.
Shift register loads the sensor value from the previous scan · case 04
A part that arrives on the same scan as the encoder edge is not tracked.
Shift register loads the sensor value from the previous scan · case 05
A part that arrives on the same scan as the encoder edge is not tracked.
Shift register unload bit is cleared between shifts · case 01
The reject solenoid only sees the unloaded part for the single edge scan.
Shift register unload bit is cleared between shifts · case 02
The reject solenoid only sees the unloaded part for the single edge scan.
Shift register unload bit is cleared between shifts · case 03
The reject solenoid only sees the unloaded part for the single edge scan.
Shift register unload bit is cleared between shifts · case 04
The reject solenoid only sees the unloaded part for the single edge scan.
Shift register unload bit is cleared between shifts · case 05
The reject solenoid only sees the unloaded part for the single edge scan.
Step sequencer cascades through several transitions in one scan · case 01
Steps whose transition is already satisfied are skipped without ever being active for a scan.
Step sequencer cascades through several transitions in one scan · case 02
Steps whose transition is already satisfied are skipped without ever being active for a scan.
Step sequencer cascades through several transitions in one scan · case 03
Steps whose transition is already satisfied are skipped without ever being active for a scan.
Step sequencer cascades through several transitions in one scan · case 04
Steps whose transition is already satisfied are skipped without ever being active for a scan.
Step sequencer cascades through several transitions in one scan · case 05
Steps whose transition is already satisfied are skipped without ever being active for a scan.
Step time includes the scan on which the step was entered · case 01
Minimum step dwell times finish one scan early.
Step time includes the scan on which the step was entered · case 02
Minimum step dwell times finish one scan early.
Step time includes the scan on which the step was entered · case 03
Minimum step dwell times finish one scan early.
Step time includes the scan on which the step was entered · case 04
Minimum step dwell times finish one scan early.
Step time includes the scan on which the step was entered · case 05
Minimum step dwell times finish one scan early.
Step transition waits for step time to exceed the minimum · case 01
Every step dwells one scan longer than its configured minimum, and zero-time steps need a scan of time.
Step transition waits for step time to exceed the minimum · case 02
Every step dwells one scan longer than its configured minimum, and zero-time steps need a scan of time.
Step transition waits for step time to exceed the minimum · case 03
Every step dwells one scan longer than its configured minimum, and zero-time steps need a scan of time.
Step transition waits for step time to exceed the minimum · case 04
Every step dwells one scan longer than its configured minimum, and zero-time steps need a scan of time.
Step transition waits for step time to exceed the minimum · case 05
Every step dwells one scan longer than its configured minimum, and zero-time steps need a scan of time.
Step sequence stalls on its last step · case 01
After the final step the sequence never returns to the initial step.
Step sequence stalls on its last step · case 02
After the final step the sequence never returns to the initial step.
Step sequence stalls on its last step · case 03
After the final step the sequence never returns to the initial step.
Step sequence stalls on its last step · case 04
After the final step the sequence never returns to the initial step.
Step sequence stalls on its last step · case 05
After the final step the sequence never returns to the initial step.
New step inherits the previous step's excess time · case 01
A step can transition earlier than its minimum because leftover time from the previous step is carried in.
New step inherits the previous step's excess time · case 02
A step can transition earlier than its minimum because leftover time from the previous step is carried in.
New step inherits the previous step's excess time · case 03
A step can transition earlier than its minimum because leftover time from the previous step is carried in.
New step inherits the previous step's excess time · case 04
A step can transition earlier than its minimum because leftover time from the previous step is carried in.
New step inherits the previous step's excess time · case 05
A step can transition earlier than its minimum because leftover time from the previous step is carried in.
FIFO load overwrites the newest entry when full · case 01
A part queued while the FIFO is full replaces the last queued part instead of being rejected.
FIFO load overwrites the newest entry when full · case 02
A part queued while the FIFO is full replaces the last queued part instead of being rejected.
FIFO load overwrites the newest entry when full · case 03
A part queued while the FIFO is full replaces the last queued part instead of being rejected.
FIFO load overwrites the newest entry when full · case 04
A part queued while the FIFO is full replaces the last queued part instead of being rejected.
FIFO load overwrites the newest entry when full · case 05
A part queued while the FIFO is full replaces the last queued part instead of being rejected.
FIFO unload returns the most recent entry · case 01
Parts leave the queue last-in first-out.
FIFO unload returns the most recent entry · case 02
Parts leave the queue last-in first-out.
FIFO unload returns the most recent entry · case 03
Parts leave the queue last-in first-out.
FIFO unload returns the most recent entry · case 04
Parts leave the queue last-in first-out.
FIFO unload returns the most recent entry · case 05
Parts leave the queue last-in first-out.
FIFO shift duplicates the last element into the vacated slot · case 01
Stale data remains visible in the file beyond the valid position.
FIFO shift duplicates the last element into the vacated slot · case 02
Stale data remains visible in the file beyond the valid position.
FIFO shift duplicates the last element into the vacated slot · case 03
Stale data remains visible in the file beyond the valid position.
FIFO shift duplicates the last element into the vacated slot · case 04
Stale data remains visible in the file beyond the valid position.
FIFO shift duplicates the last element into the vacated slot · case 05
Stale data remains visible in the file beyond the valid position.
Unloading an empty FIFO overwrites the destination · case 01
An unload request on an empty queue changes the destination word.
Unloading an empty FIFO overwrites the destination · case 02
An unload request on an empty queue changes the destination word.
Unloading an empty FIFO overwrites the destination · case 03
An unload request on an empty queue changes the destination word.
Unloading an empty FIFO overwrites the destination · case 04
An unload request on an empty queue changes the destination word.
Unloading an empty FIFO overwrites the destination · case 05
An unload request on an empty queue changes the destination word.
FIFO done bit sets one entry before full · case 01
The upstream station is told the FIFO is full while one slot is still free.
FIFO done bit sets one entry before full · case 02
The upstream station is told the FIFO is full while one slot is still free.
FIFO done bit sets one entry before full · case 03
The upstream station is told the FIFO is full while one slot is still free.
FIFO done bit sets one entry before full · case 04
The upstream station is told the FIFO is full while one slot is still free.
FIFO done bit sets one entry before full · case 05
The upstream station is told the FIFO is full while one slot is still free.
FIFO empty bit is derived from the unloaded value · case 01
EM reports empty after a zero-valued part is unloaded even though entries remain, or not empty when drained of nonzero parts.
FIFO empty bit is derived from the unloaded value · case 02
EM reports empty after a zero-valued part is unloaded even though entries remain, or not empty when drained of nonzero parts.
FIFO empty bit is derived from the unloaded value · case 03
EM reports empty after a zero-valued part is unloaded even though entries remain, or not empty when drained of nonzero parts.
FIFO empty bit is derived from the unloaded value · case 04
EM reports empty after a zero-valued part is unloaded even though entries remain, or not empty when drained of nonzero parts.
FIFO empty bit is derived from the unloaded value · case 05
EM reports empty after a zero-valued part is unloaded even though entries remain, or not empty when drained of nonzero parts.
Alarm on-delay counts non-consecutive true scans · case 01
A chattering signal raises the alarm although it was never true for the required consecutive scans.
Alarm on-delay counts non-consecutive true scans · case 02
A chattering signal raises the alarm although it was never true for the required consecutive scans.
Alarm on-delay counts non-consecutive true scans · case 03
A chattering signal raises the alarm although it was never true for the required consecutive scans.
Alarm on-delay counts non-consecutive true scans · case 04
A chattering signal raises the alarm although it was never true for the required consecutive scans.
Alarm on-delay counts non-consecutive true scans · case 05
A chattering signal raises the alarm although it was never true for the required consecutive scans.
Alarm activates one scan after its minimum duration · case 01
Every alarm is announced one scan late.
Alarm activates one scan after its minimum duration · case 02
Every alarm is announced one scan late.
Alarm activates one scan after its minimum duration · case 03
Every alarm is announced one scan late.
Alarm activates one scan after its minimum duration · case 04
Every alarm is announced one scan late.
Alarm activates one scan after its minimum duration · case 05
Every alarm is announced one scan late.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗