FAILURE MAP

Understand the failure.
Verify the repair.

Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.

Explore the cases ↓How results are verified ↗
100840Executable case variants
20168Distinct failure mechanisms
302520Executed implementations
20168Open-access cases

WHAT THE ARCHIVE CONTAINS

100840 executable cases. 20168 are open.

Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.

The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗

A RECORD OF WHAT WENT WRONG

Browse the archive / 100840

Python · Standard library
REFERENCEFAILURE MECHANISMDOMAINACCESS
FA-89201

Unknown toggle enable holds the flop · case 01

A T flip-flop with T='x' keeps its value instead of going unknown.

Digital logic simulation● Open access↗
FA-89202

Unknown toggle enable holds the flop · case 02

A T flip-flop with T='x' keeps its value instead of going unknown.

Digital logic simulation◈ Members↗
FA-89203

Unknown toggle enable holds the flop · case 03

A T flip-flop with T='x' keeps its value instead of going unknown.

Digital logic simulation◈ Members↗
FA-89204

Unknown toggle enable holds the flop · case 04

A T flip-flop with T='x' keeps its value instead of going unknown.

Digital logic simulation◈ Members↗
FA-89205

Unknown toggle enable holds the flop · case 05

A T flip-flop with T='x' keeps its value instead of going unknown.

Digital logic simulation◈ Members↗
FA-89206

Transitions through unknown counted as full toggles · case 01

Energy is overestimated for nets that pass through x.

Digital logic simulation● Open access↗
FA-89207

Transitions through unknown counted as full toggles · case 02

Energy is overestimated for nets that pass through x.

Digital logic simulation◈ Members↗
FA-89208

Transitions through unknown counted as full toggles · case 03

Energy is overestimated for nets that pass through x.

Digital logic simulation◈ Members↗
FA-89209

Transitions through unknown counted as full toggles · case 04

Energy is overestimated for nets that pass through x.

Digital logic simulation◈ Members↗
FA-89210

Transitions through unknown counted as full toggles · case 05

Energy is overestimated for nets that pass through x.

Digital logic simulation◈ Members↗
FA-89211

Functional toggle taken from the first value of a cycle · case 01

Glitchy cycles report functional activity based on a transient value rather than the settled value.

Digital logic simulation● Open access↗
FA-89212

Functional toggle taken from the first value of a cycle · case 02

Glitchy cycles report functional activity based on a transient value rather than the settled value.

Digital logic simulation◈ Members↗
FA-89213

Functional toggle taken from the first value of a cycle · case 03

Glitchy cycles report functional activity based on a transient value rather than the settled value.

Digital logic simulation◈ Members↗
FA-89214

Functional toggle taken from the first value of a cycle · case 04

Glitchy cycles report functional activity based on a transient value rather than the settled value.

Digital logic simulation◈ Members↗
FA-89215

Functional toggle taken from the first value of a cycle · case 05

Glitchy cycles report functional activity based on a transient value rather than the settled value.

Digital logic simulation◈ Members↗
FA-89216

Glitch reference reset at every cycle boundary · case 01

Total energy counts transitions from the initial value at each cycle start instead of from the last event.

Digital logic simulation● Open access↗
FA-89217

Glitch reference reset at every cycle boundary · case 02

Total energy counts transitions from the initial value at each cycle start instead of from the last event.

Digital logic simulation◈ Members↗
FA-89218

Glitch reference reset at every cycle boundary · case 03

Total energy counts transitions from the initial value at each cycle start instead of from the last event.

Digital logic simulation◈ Members↗
FA-89219

Glitch reference reset at every cycle boundary · case 04

Total energy counts transitions from the initial value at each cycle start instead of from the last event.

Digital logic simulation◈ Members↗
FA-89220

Glitch reference reset at every cycle boundary · case 05

Total energy counts transitions from the initial value at each cycle start instead of from the last event.

Digital logic simulation◈ Members↗
FA-89221

Unannotated nets charged unit capacitance · case 01

Nets without a capacitance annotation add energy to the estimate.

Digital logic simulation● Open access↗
FA-89222

Unannotated nets charged unit capacitance · case 02

Nets without a capacitance annotation add energy to the estimate.

Digital logic simulation◈ Members↗
FA-89223

Unannotated nets charged unit capacitance · case 03

Nets without a capacitance annotation add energy to the estimate.

Digital logic simulation◈ Members↗
FA-89224

Unannotated nets charged unit capacitance · case 04

Nets without a capacitance annotation add energy to the estimate.

Digital logic simulation◈ Members↗
FA-89225

Unannotated nets charged unit capacitance · case 05

Nets without a capacitance annotation add energy to the estimate.

Digital logic simulation◈ Members↗
FA-89226

Unknown select bit treated as zero · case 01

A multiplexer with an unknown select passes input 0 instead of merging candidates.

Digital logic simulation● Open access↗
FA-89227

Unknown select bit treated as zero · case 02

A multiplexer with an unknown select passes input 0 instead of merging candidates.

Digital logic simulation◈ Members↗
FA-89228

Unknown select bit treated as zero · case 03

A multiplexer with an unknown select passes input 0 instead of merging candidates.

Digital logic simulation◈ Members↗
FA-89229

Unknown select bit treated as zero · case 04

A multiplexer with an unknown select passes input 0 instead of merging candidates.

Digital logic simulation◈ Members↗
FA-89230

Unknown select bit treated as zero · case 05

A multiplexer with an unknown select passes input 0 instead of merging candidates.

Digital logic simulation◈ Members↗
FA-89231

Agreeing floating inputs pass through an unknown select · case 01

Two candidate inputs both at 'z' produce 'z' instead of 'x'.

Digital logic simulation● Open access↗
FA-89232

Agreeing floating inputs pass through an unknown select · case 02

Two candidate inputs both at 'z' produce 'z' instead of 'x'.

Digital logic simulation◈ Members↗
FA-89233

Agreeing floating inputs pass through an unknown select · case 03

Two candidate inputs both at 'z' produce 'z' instead of 'x'.

Digital logic simulation◈ Members↗
FA-89234

Agreeing floating inputs pass through an unknown select · case 04

Two candidate inputs both at 'z' produce 'z' instead of 'x'.

Digital logic simulation◈ Members↗
FA-89235

Agreeing floating inputs pass through an unknown select · case 05

Two candidate inputs both at 'z' produce 'z' instead of 'x'.

Digital logic simulation◈ Members↗
FA-89236

Unknown select corrupts every decoder line · case 01

A decoder with one unknown select bit drives x on lines that cannot be selected.

Digital logic simulation● Open access↗
FA-89237

Unknown select corrupts every decoder line · case 02

A decoder with one unknown select bit drives x on lines that cannot be selected.

Digital logic simulation◈ Members↗
FA-89238

Unknown select corrupts every decoder line · case 03

A decoder with one unknown select bit drives x on lines that cannot be selected.

Digital logic simulation◈ Members↗
FA-89239

Unknown select corrupts every decoder line · case 04

A decoder with one unknown select bit drives x on lines that cannot be selected.

Digital logic simulation◈ Members↗
FA-89240

Unknown select corrupts every decoder line · case 05

A decoder with one unknown select bit drives x on lines that cannot be selected.

Digital logic simulation◈ Members↗
FA-89241

Unknown decoder enable treated as asserted · case 01

With enable 'x' the selected line reads 1.

Digital logic simulation● Open access↗
FA-89242

Unknown decoder enable treated as asserted · case 02

With enable 'x' the selected line reads 1.

Digital logic simulation◈ Members↗
FA-89243

Unknown decoder enable treated as asserted · case 03

With enable 'x' the selected line reads 1.

Digital logic simulation◈ Members↗
FA-89244

Unknown decoder enable treated as asserted · case 04

With enable 'x' the selected line reads 1.

Digital logic simulation◈ Members↗
FA-89245

Unknown decoder enable treated as asserted · case 05

With enable 'x' the selected line reads 1.

Digital logic simulation◈ Members↗
FA-89246

Up count reaches the modulus before wrapping · case 01

The counter visits the value m before returning to 0.

Digital logic simulation● Open access↗
FA-89247

Up count reaches the modulus before wrapping · case 02

The counter visits the value m before returning to 0.

Digital logic simulation◈ Members↗
FA-89248

Up count reaches the modulus before wrapping · case 03

The counter visits the value m before returning to 0.

Digital logic simulation◈ Members↗
FA-89249

Up count reaches the modulus before wrapping · case 04

The counter visits the value m before returning to 0.

Digital logic simulation◈ Members↗
FA-89250

Up count reaches the modulus before wrapping · case 05

The counter visits the value m before returning to 0.

Digital logic simulation◈ Members↗
FA-89251

Down count saturates at zero · case 01

Counting down from 0 stays at 0 instead of wrapping to m-1.

Digital logic simulation● Open access↗
FA-89252

Down count saturates at zero · case 02

Counting down from 0 stays at 0 instead of wrapping to m-1.

Digital logic simulation◈ Members↗
FA-89253

Down count saturates at zero · case 03

Counting down from 0 stays at 0 instead of wrapping to m-1.

Digital logic simulation◈ Members↗
FA-89254

Down count saturates at zero · case 04

Counting down from 0 stays at 0 instead of wrapping to m-1.

Digital logic simulation◈ Members↗
FA-89255

Down count saturates at zero · case 05

Counting down from 0 stays at 0 instead of wrapping to m-1.

Digital logic simulation◈ Members↗
FA-89256

Terminal count asserted while the counter is disabled · case 01

tc is high whenever the counter sits at its terminal value, even with enable low.

Digital logic simulation● Open access↗
FA-89257

Terminal count asserted while the counter is disabled · case 02

tc is high whenever the counter sits at its terminal value, even with enable low.

Digital logic simulation◈ Members↗
FA-89258

Terminal count asserted while the counter is disabled · case 03

tc is high whenever the counter sits at its terminal value, even with enable low.

Digital logic simulation◈ Members↗
FA-89259

Terminal count asserted while the counter is disabled · case 04

tc is high whenever the counter sits at its terminal value, even with enable low.

Digital logic simulation◈ Members↗
FA-89260

Terminal count asserted while the counter is disabled · case 05

tc is high whenever the counter sits at its terminal value, even with enable low.

Digital logic simulation◈ Members↗
FA-89261

Load ignored while count enable is low · case 01

A synchronous load issued with enable low does not change the counter.

Digital logic simulation● Open access↗
FA-89262

Load ignored while count enable is low · case 02

A synchronous load issued with enable low does not change the counter.

Digital logic simulation◈ Members↗
FA-89263

Load ignored while count enable is low · case 03

A synchronous load issued with enable low does not change the counter.

Digital logic simulation◈ Members↗
FA-89264

Load ignored while count enable is low · case 04

A synchronous load issued with enable low does not change the counter.

Digital logic simulation◈ Members↗
FA-89265

Load ignored while count enable is low · case 05

A synchronous load issued with enable low does not change the counter.

Digital logic simulation◈ Members↗
FA-89266

Out-of-range load value stored directly · case 01

Loading a value above the modulus puts the counter in an illegal state.

Digital logic simulation● Open access↗
FA-89267

Out-of-range load value stored directly · case 02

Loading a value above the modulus puts the counter in an illegal state.

Digital logic simulation◈ Members↗
FA-89268

Out-of-range load value stored directly · case 03

Loading a value above the modulus puts the counter in an illegal state.

Digital logic simulation◈ Members↗
FA-89269

Out-of-range load value stored directly · case 04

Loading a value above the modulus puts the counter in an illegal state.

Digital logic simulation◈ Members↗
FA-89270

Out-of-range load value stored directly · case 05

Loading a value above the modulus puts the counter in an illegal state.

Digital logic simulation◈ Members↗
FA-89271

Scan data shifted toward the scan input · case 01

The chain moves data backwards and scan-in enters at the scan-out end.

Digital logic simulation● Open access↗
FA-89272

Scan data shifted toward the scan input · case 02

The chain moves data backwards and scan-in enters at the scan-out end.

Digital logic simulation◈ Members↗
FA-89273

Scan data shifted toward the scan input · case 03

The chain moves data backwards and scan-in enters at the scan-out end.

Digital logic simulation◈ Members↗
FA-89274

Scan data shifted toward the scan input · case 04

The chain moves data backwards and scan-in enters at the scan-out end.

Digital logic simulation◈ Members↗
FA-89275

Scan data shifted toward the scan input · case 05

The chain moves data backwards and scan-in enters at the scan-out end.

Digital logic simulation◈ Members↗
FA-89276

Scan-out observed after the shift edge · case 01

The unloaded bit stream is missing the first bit and one position late.

Digital logic simulation● Open access↗
FA-89277

Scan-out observed after the shift edge · case 02

The unloaded bit stream is missing the first bit and one position late.

Digital logic simulation◈ Members↗
FA-89278

Scan-out observed after the shift edge · case 03

The unloaded bit stream is missing the first bit and one position late.

Digital logic simulation◈ Members↗
FA-89279

Scan-out observed after the shift edge · case 04

The unloaded bit stream is missing the first bit and one position late.

Digital logic simulation◈ Members↗
FA-89280

Scan-out observed after the shift edge · case 05

The unloaded bit stream is missing the first bit and one position late.

Digital logic simulation◈ Members↗
FA-89281

Shift updates flops in place from the scan input · case 01

One shift fills the entire chain with the scan-in bit.

Digital logic simulation● Open access↗
FA-89282

Shift updates flops in place from the scan input · case 02

One shift fills the entire chain with the scan-in bit.

Digital logic simulation◈ Members↗
FA-89283

Shift updates flops in place from the scan input · case 03

One shift fills the entire chain with the scan-in bit.

Digital logic simulation◈ Members↗
FA-89284

Shift updates flops in place from the scan input · case 04

One shift fills the entire chain with the scan-in bit.

Digital logic simulation◈ Members↗
FA-89285

Shift updates flops in place from the scan input · case 05

One shift fills the entire chain with the scan-in bit.

Digital logic simulation◈ Members↗
FA-89286

Capture evaluates next state from partially updated flops · case 01

Flops later in the chain capture values computed from already-updated earlier flops.

Digital logic simulation● Open access↗
FA-89287

Capture evaluates next state from partially updated flops · case 02

Flops later in the chain capture values computed from already-updated earlier flops.

Digital logic simulation◈ Members↗
FA-89288

Capture evaluates next state from partially updated flops · case 03

Flops later in the chain capture values computed from already-updated earlier flops.

Digital logic simulation◈ Members↗
FA-89289

Capture evaluates next state from partially updated flops · case 04

Flops later in the chain capture values computed from already-updated earlier flops.

Digital logic simulation◈ Members↗
FA-89290

Capture evaluates next state from partially updated flops · case 05

Flops later in the chain capture values computed from already-updated earlier flops.

Digital logic simulation◈ Members↗
FA-89291

Gated clock uses the raw enable · case 01

Changing enable while the clock is high chops or creates clock pulses.

Digital logic simulation● Open access↗
FA-89292

Gated clock uses the raw enable · case 02

Changing enable while the clock is high chops or creates clock pulses.

Digital logic simulation◈ Members↗
FA-89293

Gated clock uses the raw enable · case 03

Changing enable while the clock is high chops or creates clock pulses.

Digital logic simulation◈ Members↗
FA-89294

Gated clock uses the raw enable · case 04

Changing enable while the clock is high chops or creates clock pulses.

Digital logic simulation◈ Members↗
FA-89295

Gated clock uses the raw enable · case 05

Changing enable while the clock is high chops or creates clock pulses.

Digital logic simulation◈ Members↗
FA-89296

Enable latch transparent during clock high · case 01

The gated clock follows enable changes during the high phase.

Digital logic simulation● Open access↗
FA-89297

Enable latch transparent during clock high · case 02

The gated clock follows enable changes during the high phase.

Digital logic simulation◈ Members↗
FA-89298

Enable latch transparent during clock high · case 03

The gated clock follows enable changes during the high phase.

Digital logic simulation◈ Members↗
FA-89299

Enable latch transparent during clock high · case 04

The gated clock follows enable changes during the high phase.

Digital logic simulation◈ Members↗
FA-89300

Enable latch transparent during clock high · case 05

The gated clock follows enable changes during the high phase.

Digital logic simulation◈ Members↗

INSPECTABLE BY DESIGN

Every result has a runnable source.

Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.

Read the methodology ↗