FA-89248 / Digital logic simulation / Member archive

Up count reaches the modulus before wrapping · case 03

The counter visits the value m before returning to 0.

Member previewVariant 3 · 3 implementations · 7 checks per implementation

Case contract

Input [m, q0, ops]: ops per clock [load, value, en, up]. Before the edge tc = en==1 and ((up==1 and q==m-1) or (up==0 and q==0)). At the edge load==1 sets q = value mod m (load has priority and ignores en); else en==1 counts up or down modulo m. Return [q after edge, tc] per clock.

Why this case matters

Counters are the most common sequential primitive; wrap, load priority and terminal-count gating are recurring simulation-model bugs.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
count up through wrap	`[[5, 0], [6, 1], [0, 0], [1, 0]]`	`[[5, 0], [0, 1], [1, 0], [2, 0]]`	Failed

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