FA-89280 / Digital logic simulation / Member archive

Scan-out observed after the shift edge · case 05

The unloaded bit stream is missing the first bit and one position late.

Member previewVariant 5 · 3 implementations · 6 checks per implementation

Case contract

Input [chain, logic, state, ops]: chain lists flops from scan-in to scan-out. 'shift' with bit b: scan-out observes the last flop before the edge, then every flop takes its predecessor's old value and the first takes b. 'capture': every flop loads its functional next state logic[f] = [op, inputs] (and/xor/not) computed from the old state of all flops simultaneously. Return [scan-out bits, final chain values].

Why this case matters

Scan-based test simulation must shift and capture as simultaneous register updates.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
shift in a pattern	`[[1, 0, 1], [1, 0, 1, 1]]`	`[[1, 1, 0], [1, 0, 1, 1]]`	Failed

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