Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Scan test enable not ORed into the latch · case 01
With te=1 and en=0 the gated clock stays low during scan shift.
Scan test enable not ORed into the latch · case 02
With te=1 and en=0 the gated clock stays low during scan shift.
Scan test enable not ORed into the latch · case 03
With te=1 and en=0 the gated clock stays low during scan shift.
Scan test enable not ORed into the latch · case 04
With te=1 and en=0 the gated clock stays low during scan shift.
Scan test enable not ORed into the latch · case 05
With te=1 and en=0 the gated clock stays low during scan shift.
Gated clock edges counted as high samples · case 01
A gated pulse spanning several samples is counted several times.
Gated clock edges counted as high samples · case 02
A gated pulse spanning several samples is counted several times.
Gated clock edges counted as high samples · case 03
A gated pulse spanning several samples is counted several times.
Gated clock edges counted as high samples · case 04
A gated pulse spanning several samples is counted several times.
Gated clock edges counted as high samples · case 05
A gated pulse spanning several samples is counted several times.
Enable latch powers up open · case 01
A clock high in the very first sample passes through before the latch has captured an enable.
Enable latch powers up open · case 02
A clock high in the very first sample passes through before the latch has captured an enable.
Enable latch powers up open · case 03
A clock high in the very first sample passes through before the latch has captured an enable.
Enable latch powers up open · case 04
A clock high in the very first sample passes through before the latch has captured an enable.
Enable latch powers up open · case 05
A clock high in the very first sample passes through before the latch has captured an enable.
Gray code computed with a left shift · case 01
The full flag never asserts at the true full condition.
Gray code computed with a left shift · case 02
The full flag never asserts at the true full condition.
Gray code computed with a left shift · case 03
The full flag never asserts at the true full condition.
Gray code computed with a left shift · case 04
The full flag never asserts at the true full condition.
Gray code computed with a left shift · case 05
The full flag never asserts at the true full condition.
Full test inverts only the gray MSB · case 01
The FIFO never reports full and overflows.
Full test inverts only the gray MSB · case 02
The FIFO never reports full and overflows.
Full test inverts only the gray MSB · case 03
The FIFO never reports full and overflows.
Full test inverts only the gray MSB · case 04
The FIFO never reports full and overflows.
Full test inverts only the gray MSB · case 05
The FIFO never reports full and overflows.
Pointer synchronizer modelled with one stage · case 01
Flags react one step early compared with a two-flop synchronizer.
Pointer synchronizer modelled with one stage · case 02
Flags react one step early compared with a two-flop synchronizer.
Pointer synchronizer modelled with one stage · case 03
Flags react one step early compared with a two-flop synchronizer.
Pointer synchronizer modelled with one stage · case 04
Flags react one step early compared with a two-flop synchronizer.
Pointer synchronizer modelled with one stage · case 05
Flags react one step early compared with a two-flop synchronizer.
Write accepted while full · case 01
Writes past full advance the pointer and corrupt the flags.
Write accepted while full · case 02
Writes past full advance the pointer and corrupt the flags.
Write accepted while full · case 03
Writes past full advance the pointer and corrupt the flags.
Write accepted while full · case 04
Writes past full advance the pointer and corrupt the flags.
Write accepted while full · case 05
Writes past full advance the pointer and corrupt the flags.
Pointers wrap at the FIFO depth · case 01
Full and empty become indistinguishable after one wrap.
Pointers wrap at the FIFO depth · case 02
Full and empty become indistinguishable after one wrap.
Pointers wrap at the FIFO depth · case 03
Full and empty become indistinguishable after one wrap.
Pointers wrap at the FIFO depth · case 04
Full and empty become indistinguishable after one wrap.
Pointers wrap at the FIFO depth · case 05
Full and empty become indistinguishable after one wrap.
SBC treats the carry flag as a borrow flag · case 01
Subtraction with carry set comes out one too small and with carry clear one too large.
SBC treats the carry flag as a borrow flag · case 02
Subtraction with carry set comes out one too small and with carry clear one too large.
SBC treats the carry flag as a borrow flag · case 03
Subtraction with carry set comes out one too small and with carry clear one too large.
SBC treats the carry flag as a borrow flag · case 04
Subtraction with carry set comes out one too small and with carry clear one too large.
SBC treats the carry flag as a borrow flag · case 05
Subtraction with carry set comes out one too small and with carry clear one too large.
Overflow flag set whenever the sign changes · case 01
Adding a positive to a negative that changes the accumulator sign reports signed overflow.
Overflow flag set whenever the sign changes · case 02
Adding a positive to a negative that changes the accumulator sign reports signed overflow.
Overflow flag set whenever the sign changes · case 03
Adding a positive to a negative that changes the accumulator sign reports signed overflow.
Overflow flag set whenever the sign changes · case 04
Adding a positive to a negative that changes the accumulator sign reports signed overflow.
Overflow flag set whenever the sign changes · case 05
Adding a positive to a negative that changes the accumulator sign reports signed overflow.
Carry set on a sum of exactly 0xFF · case 01
An addition that lands exactly on 0xFF reports carry.
Carry set on a sum of exactly 0xFF · case 02
An addition that lands exactly on 0xFF reports carry.
Carry set on a sum of exactly 0xFF · case 03
An addition that lands exactly on 0xFF reports carry.
Carry set on a sum of exactly 0xFF · case 04
An addition that lands exactly on 0xFF reports carry.
Carry set on a sum of exactly 0xFF · case 05
An addition that lands exactly on 0xFF reports carry.
CMP clears carry on equality · case 01
Comparing equal values clears carry, so a branch on carry set after CMP misses equal operands.
CMP clears carry on equality · case 02
Comparing equal values clears carry, so a branch on carry set after CMP misses equal operands.
CMP clears carry on equality · case 03
Comparing equal values clears carry, so a branch on carry set after CMP misses equal operands.
CMP clears carry on equality · case 04
Comparing equal values clears carry, so a branch on carry set after CMP misses equal operands.
CMP clears carry on equality · case 05
Comparing equal values clears carry, so a branch on carry set after CMP misses equal operands.
Zero flag computed from the 9-bit sum · case 01
An addition that wraps to 0x00 with carry does not set Z.
Zero flag computed from the 9-bit sum · case 02
An addition that wraps to 0x00 with carry does not set Z.
Zero flag computed from the 9-bit sum · case 03
An addition that wraps to 0x00 with carry does not set Z.
Zero flag computed from the 9-bit sum · case 04
An addition that wraps to 0x00 with carry does not set Z.
Zero flag computed from the 9-bit sum · case 05
An addition that wraps to 0x00 with carry does not set Z.
Branch offset applied to the opcode address · case 01
Every taken branch lands two bytes early.
Branch offset applied to the opcode address · case 02
Every taken branch lands two bytes early.
Branch offset applied to the opcode address · case 03
Every taken branch lands two bytes early.
Branch offset applied to the opcode address · case 04
Every taken branch lands two bytes early.
Branch offset applied to the opcode address · case 05
Every taken branch lands two bytes early.
Displacement 0x80 treated as positive · case 01
A branch with displacement 0x80 jumps forward 128 bytes instead of back 128.
Displacement 0x80 treated as positive · case 02
A branch with displacement 0x80 jumps forward 128 bytes instead of back 128.
Displacement 0x80 treated as positive · case 03
A branch with displacement 0x80 jumps forward 128 bytes instead of back 128.
Displacement 0x80 treated as positive · case 04
A branch with displacement 0x80 jumps forward 128 bytes instead of back 128.
Displacement 0x80 treated as positive · case 05
A branch with displacement 0x80 jumps forward 128 bytes instead of back 128.
Branch target escapes the 16-bit address space · case 01
Branches near address 0 or 0xFFFF produce negative or 17-bit targets.
Branch target escapes the 16-bit address space · case 02
Branches near address 0 or 0xFFFF produce negative or 17-bit targets.
Branch target escapes the 16-bit address space · case 03
Branches near address 0 or 0xFFFF produce negative or 17-bit targets.
Branch target escapes the 16-bit address space · case 04
Branches near address 0 or 0xFFFF produce negative or 17-bit targets.
Branch target escapes the 16-bit address space · case 05
Branches near address 0 or 0xFFFF produce negative or 17-bit targets.
Page crossing measured from the branch opcode · case 01
A branch whose opcode sits at the end of a page is charged a crossing cycle incorrectly or misses one.
Page crossing measured from the branch opcode · case 02
A branch whose opcode sits at the end of a page is charged a crossing cycle incorrectly or misses one.
Page crossing measured from the branch opcode · case 03
A branch whose opcode sits at the end of a page is charged a crossing cycle incorrectly or misses one.
Page crossing measured from the branch opcode · case 04
A branch whose opcode sits at the end of a page is charged a crossing cycle incorrectly or misses one.
Page crossing measured from the branch opcode · case 05
A branch whose opcode sits at the end of a page is charged a crossing cycle incorrectly or misses one.
Taken branch charged as not taken · case 01
Taken branches cost one cycle too few.
Taken branch charged as not taken · case 02
Taken branches cost one cycle too few.
Taken branch charged as not taken · case 03
Taken branches cost one cycle too few.
Taken branch charged as not taken · case 04
Taken branches cost one cycle too few.
Taken branch charged as not taken · case 05
Taken branches cost one cycle too few.
Push decrements before storing · case 01
Pushed bytes land one slot below where pulls read them.
Push decrements before storing · case 02
Pushed bytes land one slot below where pulls read them.
Push decrements before storing · case 03
Pushed bytes land one slot below where pulls read them.
Push decrements before storing · case 04
Pushed bytes land one slot below where pulls read them.
Push decrements before storing · case 05
Pushed bytes land one slot below where pulls read them.
Call pushes the true next-instruction address · case 01
Returning from a subroutine skips the first byte of the following instruction.
Call pushes the true next-instruction address · case 02
Returning from a subroutine skips the first byte of the following instruction.
Call pushes the true next-instruction address · case 03
Returning from a subroutine skips the first byte of the following instruction.
Call pushes the true next-instruction address · case 04
Returning from a subroutine skips the first byte of the following instruction.
Call pushes the true next-instruction address · case 05
Returning from a subroutine skips the first byte of the following instruction.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗