FA-89378 / Instruction set emulation / Member archive

Branch target escapes the 16-bit address space · case 03

Branches near address 0 or 0xFFFF produce negative or 17-bit targets.

Member previewVariant 3 · 3 implementations · 10 checks per implementation

Case contract

Input [pc, disp, taken] for a 2-byte conditional branch at pc in a 16-bit address space. The next instruction is (pc+2) & 0xFFFF; disp is an 8-bit two's complement offset from that address. Not taken: [next, 2]. Taken: target = (next + offset) & 0xFFFF and cost 3 cycles plus 1 when target and next lie on different 256-byte pages. Return [pc', cycles].

Why this case matters

Branch emulation must use the post-fetch PC, sign-extend the offset and charge page-crossing cycles exactly.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
wrap below zero	`[-121, 4]`	`[65415, 4]`	Failed

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