FA-89322 / Digital logic simulation / Member archive
Full test inverts only the gray MSB · case 02
The FIFO never reports full and overflows.
Case contract
Input [depth, ops] with depth a power of two >= 4 and ops 'w','r','n'. Pointers are binary modulo 2*depth. Each step first computes flags from gray codes (g = b ^ (b >> 1)) using the other side's pointer as it was two steps earlier: full when gray(w) equals gray(r_sync) with its top two bits inverted, empty when gray(r) equals gray(w_sync). A write happens only if not full, a read only if not empty. Return [[full, empty] per step, [writes accepted, reads accepted]].
Why this case matters
Clock-domain-crossing FIFOs are simulated with synchronizer latency; flag comparisons on gray pointers are a common source of model bugs.
One recorded failure
Sample boundary fixtureThis sample comes from the broken implementation of a controlled reproducer.
| Boundary fixture | Actual | Expected | Outcome |
|---|---|---|---|
| fill until full | [[[0, 1], [0, 1], [0, 0], [0, 0], [0, 0], [0, 0], [0, 0]], [7, 0]] | [[[0, 1], [0, 1], [0, 0], [0, 0], [1, 0], [1, 0], [1, 0]], [4, 0]] | Failed |
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