Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Unknown input bit treated as a missing transition · case 01
An 'x' input leaves the machine in a definite state instead of the unknown state.
Unknown input bit treated as a missing transition · case 02
An 'x' input leaves the machine in a definite state instead of the unknown state.
Unknown input bit treated as a missing transition · case 03
An 'x' input leaves the machine in a definite state instead of the unknown state.
Unknown input bit treated as a missing transition · case 04
An 'x' input leaves the machine in a definite state instead of the unknown state.
Unknown input bit treated as a missing transition · case 05
An 'x' input leaves the machine in a definite state instead of the unknown state.
Unknown state outputs a definite zero · case 01
While the state register is unknown the output reads 0 instead of 'x'.
Unknown state outputs a definite zero · case 02
While the state register is unknown the output reads 0 instead of 'x'.
Unknown state outputs a definite zero · case 03
While the state register is unknown the output reads 0 instead of 'x'.
Unknown state outputs a definite zero · case 04
While the state register is unknown the output reads 0 instead of 'x'.
Unknown state outputs a definite zero · case 05
While the state register is unknown the output reads 0 instead of 'x'.
Byte enable bits mapped to the wrong lanes · case 01
Writing with only the low-byte enable modifies the high byte.
Byte enable bits mapped to the wrong lanes · case 02
Writing with only the low-byte enable modifies the high byte.
Byte enable bits mapped to the wrong lanes · case 03
Writing with only the low-byte enable modifies the high byte.
Byte enable bits mapped to the wrong lanes · case 04
Writing with only the low-byte enable modifies the high byte.
Byte enable bits mapped to the wrong lanes · case 05
Writing with only the low-byte enable modifies the high byte.
Write-first RAM returns stale data · case 01
In write-first mode a read in the same cycle as a write returns the previous word.
Write-first RAM returns stale data · case 02
In write-first mode a read in the same cycle as a write returns the previous word.
Write-first RAM returns stale data · case 03
In write-first mode a read in the same cycle as a write returns the previous word.
Write-first RAM returns stale data · case 04
In write-first mode a read in the same cycle as a write returns the previous word.
Write-first RAM returns stale data · case 05
In write-first mode a read in the same cycle as a write returns the previous word.
Any byte enable writes the whole word · case 01
A single-lane write clobbers the other byte lane.
Any byte enable writes the whole word · case 02
A single-lane write clobbers the other byte lane.
Any byte enable writes the whole word · case 03
A single-lane write clobbers the other byte lane.
Any byte enable writes the whole word · case 04
A single-lane write clobbers the other byte lane.
Any byte enable writes the whole word · case 05
A single-lane write clobbers the other byte lane.
Negative address wraps to the top of memory · case 01
A write to address -1 lands in the last word.
Negative address wraps to the top of memory · case 02
A write to address -1 lands in the last word.
Negative address wraps to the top of memory · case 03
A write to address -1 lands in the last word.
Negative address wraps to the top of memory · case 04
A write to address -1 lands in the last word.
Negative address wraps to the top of memory · case 05
A write to address -1 lands in the last word.
Out-of-range read returns zero · case 01
Reading past the end of the memory yields 0 instead of 'x'.
Out-of-range read returns zero · case 02
Reading past the end of the memory yields 0 instead of 'x'.
Out-of-range read returns zero · case 03
Reading past the end of the memory yields 0 instead of 'x'.
Out-of-range read returns zero · case 04
Reading past the end of the memory yields 0 instead of 'x'.
Out-of-range read returns zero · case 05
Reading past the end of the memory yields 0 instead of 'x'.
Unchanged samples written as value changes · case 01
The dump repeats values that did not change, with extra timestamp markers.
Unchanged samples written as value changes · case 02
The dump repeats values that did not change, with extra timestamp markers.
Unchanged samples written as value changes · case 03
The dump repeats values that did not change, with extra timestamp markers.
Unchanged samples written as value changes · case 04
The dump repeats values that did not change, with extra timestamp markers.
Unchanged samples written as value changes · case 05
The dump repeats values that did not change, with extra timestamp markers.
Timestamp written for a time with only redundant samples · case 01
A '#t' marker appears for a time at which nothing changed.
Timestamp written for a time with only redundant samples · case 02
A '#t' marker appears for a time at which nothing changed.
Timestamp written for a time with only redundant samples · case 03
A '#t' marker appears for a time at which nothing changed.
Timestamp written for a time with only redundant samples · case 04
A '#t' marker appears for a time at which nothing changed.
Timestamp written for a time with only redundant samples · case 05
A '#t' marker appears for a time at which nothing changed.
All-zero vector written with no digits · case 01
A vector returning to zero is dumped as 'b <id>' with an empty value.
All-zero vector written with no digits · case 02
A vector returning to zero is dumped as 'b <id>' with an empty value.
All-zero vector written with no digits · case 03
A vector returning to zero is dumped as 'b <id>' with an empty value.
All-zero vector written with no digits · case 04
A vector returning to zero is dumped as 'b <id>' with an empty value.
All-zero vector written with no digits · case 05
A vector returning to zero is dumped as 'b <id>' with an empty value.
Short vector value printed as a scalar change · case 01
A vector sample given as a single digit is dumped in scalar form without the b prefix.
Short vector value printed as a scalar change · case 02
A vector sample given as a single digit is dumped in scalar form without the b prefix.
Short vector value printed as a scalar change · case 03
A vector sample given as a single digit is dumped in scalar form without the b prefix.
Short vector value printed as a scalar change · case 04
A vector sample given as a single digit is dumped in scalar form without the b prefix.
Short vector value printed as a scalar change · case 05
A vector sample given as a single digit is dumped in scalar form without the b prefix.
Leading unknown run not collapsed · case 01
An all-unknown vector is dumped as 'bxxx' instead of 'bx'.
Leading unknown run not collapsed · case 02
An all-unknown vector is dumped as 'bxxx' instead of 'bx'.
Leading unknown run not collapsed · case 03
An all-unknown vector is dumped as 'bxxx' instead of 'bx'.
Leading unknown run not collapsed · case 04
An all-unknown vector is dumped as 'bxxx' instead of 'bx'.
Leading unknown run not collapsed · case 05
An all-unknown vector is dumped as 'bxxx' instead of 'bx'.
Term positions read least-significant first · case 01
Hazard pairs are reported on mirrored minterm numbers.
Term positions read least-significant first · case 02
Hazard pairs are reported on mirrored minterm numbers.
Term positions read least-significant first · case 03
Hazard pairs are reported on mirrored minterm numbers.
Term positions read least-significant first · case 04
Hazard pairs are reported on mirrored minterm numbers.
Term positions read least-significant first · case 05
Hazard pairs are reported on mirrored minterm numbers.
Complemented literals ignored in term coverage · case 01
Terms with a 0 literal cover minterms where that variable is 1.
Complemented literals ignored in term coverage · case 02
Terms with a 0 literal cover minterms where that variable is 1.
Complemented literals ignored in term coverage · case 03
Terms with a 0 literal cover minterms where that variable is 1.
Complemented literals ignored in term coverage · case 04
Terms with a 0 literal cover minterms where that variable is 1.
Complemented literals ignored in term coverage · case 05
Terms with a 0 literal cover minterms where that variable is 1.
Hazard pair reported twice · case 01
Each hazard appears as both [a, b] and [b, a].
Hazard pair reported twice · case 02
Each hazard appears as both [a, b] and [b, a].
Hazard pair reported twice · case 03
Each hazard appears as both [a, b] and [b, a].
Hazard pair reported twice · case 04
Each hazard appears as both [a, b] and [b, a].
Hazard pair reported twice · case 05
Each hazard appears as both [a, b] and [b, a].
Hazard judged by first covering term only · case 01
Adjacent minterms sharing a consensus term are still reported as hazards.
Hazard judged by first covering term only · case 02
Adjacent minterms sharing a consensus term are still reported as hazards.
Hazard judged by first covering term only · case 03
Adjacent minterms sharing a consensus term are still reported as hazards.
Hazard judged by first covering term only · case 04
Adjacent minterms sharing a consensus term are still reported as hazards.
Hazard judged by first covering term only · case 05
Adjacent minterms sharing a consensus term are still reported as hazards.
Neighbour generation flips the wrong bits · case 01
Pairs that differ in more than one variable are tested and real one-bit neighbours are skipped.
Neighbour generation flips the wrong bits · case 02
Pairs that differ in more than one variable are tested and real one-bit neighbours are skipped.
Neighbour generation flips the wrong bits · case 03
Pairs that differ in more than one variable are tested and real one-bit neighbours are skipped.
Neighbour generation flips the wrong bits · case 04
Pairs that differ in more than one variable are tested and real one-bit neighbours are skipped.
Neighbour generation flips the wrong bits · case 05
Pairs that differ in more than one variable are tested and real one-bit neighbours are skipped.
JK flip-flop holds instead of toggling · case 01
J=K=1 leaves the output unchanged.
JK flip-flop holds instead of toggling · case 02
J=K=1 leaves the output unchanged.
JK flip-flop holds instead of toggling · case 03
J=K=1 leaves the output unchanged.
JK flip-flop holds instead of toggling · case 04
J=K=1 leaves the output unchanged.
JK flip-flop holds instead of toggling · case 05
J=K=1 leaves the output unchanged.
J and K inputs swapped · case 01
Asserting J clears the flop and asserting K sets it.
J and K inputs swapped · case 02
Asserting J clears the flop and asserting K sets it.
J and K inputs swapped · case 03
Asserting J clears the flop and asserting K sets it.
J and K inputs swapped · case 04
Asserting J clears the flop and asserting K sets it.
J and K inputs swapped · case 05
Asserting J clears the flop and asserting K sets it.
Forbidden SR input resolved as reset · case 01
S=R=1 produces a definite 0 instead of 'x'.
Forbidden SR input resolved as reset · case 02
S=R=1 produces a definite 0 instead of 'x'.
Forbidden SR input resolved as reset · case 03
S=R=1 produces a definite 0 instead of 'x'.
Forbidden SR input resolved as reset · case 04
S=R=1 produces a definite 0 instead of 'x'.
Forbidden SR input resolved as reset · case 05
S=R=1 produces a definite 0 instead of 'x'.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗