Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Fault detection observes only the first primary output · case 01
Faults that propagate only to later outputs are reported as undetected.
Fault detection observes only the first primary output · case 02
Faults that propagate only to later outputs are reported as undetected.
Fault detection observes only the first primary output · case 03
Faults that propagate only to later outputs are reported as undetected.
Fault detection observes only the first primary output · case 04
Faults that propagate only to later outputs are reported as undetected.
Fault detection observes only the first primary output · case 05
Faults that propagate only to later outputs are reported as undetected.
Detection index reports the last detecting vector · case 01
A fault detected by several vectors reports the last one instead of the first.
Detection index reports the last detecting vector · case 02
A fault detected by several vectors reports the last one instead of the first.
Detection index reports the last detecting vector · case 03
A fault detected by several vectors reports the last one instead of the first.
Detection index reports the last detecting vector · case 04
A fault detected by several vectors reports the last one instead of the first.
Detection index reports the last detecting vector · case 05
A fault detected by several vectors reports the last one instead of the first.
Stem faults on gate outputs are ignored · case 01
Stuck-at faults on internal gate outputs are never detected.
Stem faults on gate outputs are ignored · case 02
Stuck-at faults on internal gate outputs are never detected.
Stem faults on gate outputs are ignored · case 03
Stuck-at faults on internal gate outputs are never detected.
Stem faults on gate outputs are ignored · case 04
Stuck-at faults on internal gate outputs are never detected.
Stem faults on gate outputs are ignored · case 05
Stuck-at faults on internal gate outputs are never detected.
Driver strengths compared by name · case 01
A weak driver overrides a strong one because strengths are ordered alphabetically.
Driver strengths compared by name · case 02
A weak driver overrides a strong one because strengths are ordered alphabetically.
Driver strengths compared by name · case 03
A weak driver overrides a strong one because strengths are ordered alphabetically.
Driver strengths compared by name · case 04
A weak driver overrides a strong one because strengths are ordered alphabetically.
Driver strengths compared by name · case 05
A weak driver overrides a strong one because strengths are ordered alphabetically.
Last equal-strength driver wins contention · case 01
Two strong drivers fighting yield the value of whichever is listed last instead of x.
Last equal-strength driver wins contention · case 02
Two strong drivers fighting yield the value of whichever is listed last instead of x.
Last equal-strength driver wins contention · case 03
Two strong drivers fighting yield the value of whichever is listed last instead of x.
Last equal-strength driver wins contention · case 04
Two strong drivers fighting yield the value of whichever is listed last instead of x.
Last equal-strength driver wins contention · case 05
Two strong drivers fighting yield the value of whichever is listed last instead of x.
Released drivers still take part in resolution · case 01
A strong driver in high impedance beats an active weak driver and the net reads 'z' or 'x'.
Released drivers still take part in resolution · case 02
A strong driver in high impedance beats an active weak driver and the net reads 'z' or 'x'.
Released drivers still take part in resolution · case 03
A strong driver in high impedance beats an active weak driver and the net reads 'z' or 'x'.
Released drivers still take part in resolution · case 04
A strong driver in high impedance beats an active weak driver and the net reads 'z' or 'x'.
Released drivers still take part in resolution · case 05
A strong driver in high impedance beats an active weak driver and the net reads 'z' or 'x'.
Bus keeper value lost when all drivers release · case 01
A kept bus reads 'z' after its drivers tri-state.
Bus keeper value lost when all drivers release · case 02
A kept bus reads 'z' after its drivers tri-state.
Bus keeper value lost when all drivers release · case 03
A kept bus reads 'z' after its drivers tri-state.
Bus keeper value lost when all drivers release · case 04
A kept bus reads 'z' after its drivers tri-state.
Bus keeper value lost when all drivers release · case 05
A kept bus reads 'z' after its drivers tri-state.
Weak unknown driver poisons a strongly driven net · case 01
An unknown value from a weaker driver turns a strongly driven net into x.
Weak unknown driver poisons a strongly driven net · case 02
An unknown value from a weaker driver turns a strongly driven net into x.
Weak unknown driver poisons a strongly driven net · case 03
An unknown value from a weaker driver turns a strongly driven net into x.
Weak unknown driver poisons a strongly driven net · case 04
An unknown value from a weaker driver turns a strongly driven net into x.
Weak unknown driver poisons a strongly driven net · case 05
An unknown value from a weaker driver turns a strongly driven net into x.
Non-blocking assignment updates immediately · case 01
A register swap written with non-blocking assignments copies one value into both registers.
Non-blocking assignment updates immediately · case 02
A register swap written with non-blocking assignments copies one value into both registers.
Non-blocking assignment updates immediately · case 03
A register swap written with non-blocking assignments copies one value into both registers.
Non-blocking assignment updates immediately · case 04
A register swap written with non-blocking assignments copies one value into both registers.
Non-blocking assignment updates immediately · case 05
A register swap written with non-blocking assignments copies one value into both registers.
First queued non-blocking write wins · case 01
With two non-blocking writes to one register, the earlier write sticks.
First queued non-blocking write wins · case 02
With two non-blocking writes to one register, the earlier write sticks.
First queued non-blocking write wins · case 03
With two non-blocking writes to one register, the earlier write sticks.
First queued non-blocking write wins · case 04
With two non-blocking writes to one register, the earlier write sticks.
First queued non-blocking write wins · case 05
With two non-blocking writes to one register, the earlier write sticks.
Blocking chain reads stale pre-step values · case 01
A value computed by a blocking statement is not visible to the next statement in the same step.
Blocking chain reads stale pre-step values · case 02
A value computed by a blocking statement is not visible to the next statement in the same step.
Blocking chain reads stale pre-step values · case 03
A value computed by a blocking statement is not visible to the next statement in the same step.
Blocking chain reads stale pre-step values · case 04
A value computed by a blocking statement is not visible to the next statement in the same step.
Blocking chain reads stale pre-step values · case 05
A value computed by a blocking statement is not visible to the next statement in the same step.
Blocking-assigned variables forget their value between steps · case 01
A variable updated only by blocking assignment restarts from its initial value every step.
Blocking-assigned variables forget their value between steps · case 02
A variable updated only by blocking assignment restarts from its initial value every step.
Blocking-assigned variables forget their value between steps · case 03
A variable updated only by blocking assignment restarts from its initial value every step.
Blocking-assigned variables forget their value between steps · case 04
A variable updated only by blocking assignment restarts from its initial value every step.
Blocking-assigned variables forget their value between steps · case 05
A variable updated only by blocking assignment restarts from its initial value every step.
Floating value treated as logic high · case 01
Transitions into z are classified as rising and z->1 is not an edge.
Floating value treated as logic high · case 02
Transitions into z are classified as rising and z->1 is not an edge.
Floating value treated as logic high · case 03
Transitions into z are classified as rising and z->1 is not an edge.
Floating value treated as logic high · case 04
Transitions into z are classified as rising and z->1 is not an edge.
Floating value treated as logic high · case 05
Transitions into z are classified as rising and z->1 is not an edge.
Unknown to floating counted as a rising edge · case 01
An x->z or z->x transition triggers posedge event controls.
Unknown to floating counted as a rising edge · case 02
An x->z or z->x transition triggers posedge event controls.
Unknown to floating counted as a rising edge · case 03
An x->z or z->x transition triggers posedge event controls.
Unknown to floating counted as a rising edge · case 04
An x->z or z->x transition triggers posedge event controls.
Unknown to floating counted as a rising edge · case 05
An x->z or z->x transition triggers posedge event controls.
First sample treated as a transition from unknown · case 01
A signal that starts at 1 or 0 reports an edge at index 0.
First sample treated as a transition from unknown · case 02
A signal that starts at 1 or 0 reports an edge at index 0.
First sample treated as a transition from unknown · case 03
A signal that starts at 1 or 0 reports an edge at index 0.
First sample treated as a transition from unknown · case 04
A signal that starts at 1 or 0 reports an edge at index 0.
First sample treated as a transition from unknown · case 05
A signal that starts at 1 or 0 reports an edge at index 0.
Only 0 to 1 counted as a rising edge · case 01
Rising transitions through unknown values (0->x, x->1, z->1) do not trigger posedge.
Only 0 to 1 counted as a rising edge · case 02
Rising transitions through unknown values (0->x, x->1, z->1) do not trigger posedge.
Only 0 to 1 counted as a rising edge · case 03
Rising transitions through unknown values (0->x, x->1, z->1) do not trigger posedge.
Only 0 to 1 counted as a rising edge · case 04
Rising transitions through unknown values (0->x, x->1, z->1) do not trigger posedge.
Only 0 to 1 counted as a rising edge · case 05
Rising transitions through unknown values (0->x, x->1, z->1) do not trigger posedge.
Falling edges into unknown are missed · case 01
1->x and 1->z transitions are not reported as negedges.
Falling edges into unknown are missed · case 02
1->x and 1->z transitions are not reported as negedges.
Falling edges into unknown are missed · case 03
1->x and 1->z transitions are not reported as negedges.
Falling edges into unknown are missed · case 04
1->x and 1->z transitions are not reported as negedges.
Falling edges into unknown are missed · case 05
1->x and 1->z transitions are not reported as negedges.
Moore output taken after the state update · case 01
Outputs appear one cycle early, behaving like a Mealy machine.
Moore output taken after the state update · case 02
Outputs appear one cycle early, behaving like a Mealy machine.
Moore output taken after the state update · case 03
Outputs appear one cycle early, behaving like a Mealy machine.
Moore output taken after the state update · case 04
Outputs appear one cycle early, behaving like a Mealy machine.
Moore output taken after the state update · case 05
Outputs appear one cycle early, behaving like a Mealy machine.
Synchronous reset changes the output in the same cycle · case 01
The reset state output appears in the cycle reset is asserted instead of the following cycle.
Synchronous reset changes the output in the same cycle · case 02
The reset state output appears in the cycle reset is asserted instead of the following cycle.
Synchronous reset changes the output in the same cycle · case 03
The reset state output appears in the cycle reset is asserted instead of the following cycle.
Synchronous reset changes the output in the same cycle · case 04
The reset state output appears in the cycle reset is asserted instead of the following cycle.
Synchronous reset changes the output in the same cycle · case 05
The reset state output appears in the cycle reset is asserted instead of the following cycle.
Missing transition returns to the start state · case 01
An input with no listed transition resets the machine instead of holding its state.
Missing transition returns to the start state · case 02
An input with no listed transition resets the machine instead of holding its state.
Missing transition returns to the start state · case 03
An input with no listed transition resets the machine instead of holding its state.
Missing transition returns to the start state · case 04
An input with no listed transition resets the machine instead of holding its state.
Missing transition returns to the start state · case 05
An input with no listed transition resets the machine instead of holding its state.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗