FA-89048 / Digital logic simulation / Member archive

First queued non-blocking write wins · case 03

With two non-blocking writes to one register, the earlier write sticks.

Member previewVariant 3 · 3 implementations · 6 checks per implementation

Case contract

Input [regs, stmts, cycles]. Each clock step executes stmts [kind, lhs, op, a, b] in order (ops copy/inv/and/xor on 0/1). Blocking ('b') statements update the working state immediately; non-blocking ('nb') statements evaluate their right side at the statement against the working state and queue the update. After all statements, queued updates apply in statement order (last write wins). Every variable, blocking or not, keeps its value into the next step. Return per-step values sorted by variable name.

Why this case matters

Event-driven RTL simulation depends on the active/NBA region split; mis-scheduling produces races that do not exist in hardware.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
later non-blocking write wins	`[[0, 1], [1, 0], [0, 1], [1, 0]]`	`[[0, 0], [1, 1], [0, 0], [1, 1]]`	Failed

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