FA-89092 / Digital logic simulation / Member archive

Synchronous reset changes the output in the same cycle · case 02

The reset state output appears in the cycle reset is asserted instead of the following cycle.

Member previewVariant 2 · 3 implementations · 7 checks per implementation

Case contract

Input [table, start, stream]: table[state] = {'out': o, 'next': {bit: state}}; stream items are [bit, rst] with bit 0/1/'x'. Each cycle outputs the current state's output (or 'x' in the unknown state 'X'), then clocks: rst==1 -> start (synchronous), else unknown input or state 'X' -> 'X', else follow next[bit], staying put if that transition is absent. Return [outputs, final state].

Why this case matters

Cycle-based simulators must emit Moore outputs from the pre-edge state and model unknown propagation through state registers.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
reset while in output state	`[[0, 0, 0, 0, 0, 1], "C"]`	`[[0, 0, 1, 0, 0, 1], "C"]`	Failed

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