Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Undriven net reported as a combinational loop · case 01
A gate reading a net that nobody drives is reported as 'loop' because the gate never becomes ready.
Undriven net reported as a combinational loop · case 02
A gate reading a net that nobody drives is reported as 'loop' because the gate never becomes ready.
Undriven net reported as a combinational loop · case 03
A gate reading a net that nobody drives is reported as 'loop' because the gate never becomes ready.
Undriven net reported as a combinational loop · case 04
A gate reading a net that nobody drives is reported as 'loop' because the gate never becomes ready.
Undriven net reported as a combinational loop · case 05
A gate reading a net that nobody drives is reported as 'loop' because the gate never becomes ready.
Second driver silently overwrites a net · case 01
Two gates driving the same net are accepted and the later one wins.
Second driver silently overwrites a net · case 02
Two gates driving the same net are accepted and the later one wins.
Second driver silently overwrites a net · case 03
Two gates driving the same net are accepted and the later one wins.
Second driver silently overwrites a net · case 04
Two gates driving the same net are accepted and the later one wins.
Second driver silently overwrites a net · case 05
Two gates driving the same net are accepted and the later one wins.
NAND cell evaluated as NOR · case 01
A NAND gate with mixed inputs evaluates to 0.
NAND cell evaluated as NOR · case 02
A NAND gate with mixed inputs evaluates to 0.
NAND cell evaluated as NOR · case 03
A NAND gate with mixed inputs evaluates to 0.
NAND cell evaluated as NOR · case 04
A NAND gate with mixed inputs evaluates to 0.
NAND cell evaluated as NOR · case 05
A NAND gate with mixed inputs evaluates to 0.
Asynchronous reset waits for a clock edge · case 01
Asserting reset between clock edges leaves q at its old value until the next rising edge.
Asynchronous reset waits for a clock edge · case 02
Asserting reset between clock edges leaves q at its old value until the next rising edge.
Asynchronous reset waits for a clock edge · case 03
Asserting reset between clock edges leaves q at its old value until the next rising edge.
Asynchronous reset waits for a clock edge · case 04
Asserting reset between clock edges leaves q at its old value until the next rising edge.
Asynchronous reset waits for a clock edge · case 05
Asserting reset between clock edges leaves q at its old value until the next rising edge.
Flop captures while the clock is high · case 01
q follows d on every sample the clock is high rather than only at the rising edge.
Flop captures while the clock is high · case 02
q follows d on every sample the clock is high rather than only at the rising edge.
Flop captures while the clock is high · case 03
q follows d on every sample the clock is high rather than only at the rising edge.
Flop captures while the clock is high · case 04
q follows d on every sample the clock is high rather than only at the rising edge.
Flop captures while the clock is high · case 05
q follows d on every sample the clock is high rather than only at the rising edge.
Clock history frozen while reset is asserted · case 01
Releasing reset while the clock is already high produces a phantom capture edge.
Clock history frozen while reset is asserted · case 02
Releasing reset while the clock is already high produces a phantom capture edge.
Clock history frozen while reset is asserted · case 03
Releasing reset while the clock is already high produces a phantom capture edge.
Clock history frozen while reset is asserted · case 04
Releasing reset while the clock is already high produces a phantom capture edge.
Clock history frozen while reset is asserted · case 05
Releasing reset while the clock is already high produces a phantom capture edge.
Flop powers up as logic zero · case 01
Before any reset or capture the register reports 0 instead of unknown.
Flop powers up as logic zero · case 02
Before any reset or capture the register reports 0 instead of unknown.
Flop powers up as logic zero · case 03
Before any reset or capture the register reports 0 instead of unknown.
Flop powers up as logic zero · case 04
Before any reset or capture the register reports 0 instead of unknown.
Flop powers up as logic zero · case 05
Before any reset or capture the register reports 0 instead of unknown.
Clock capture overrides an asserted reset · case 01
A rising edge while reset is held loads d, so q is not 0 during reset.
Clock capture overrides an asserted reset · case 02
A rising edge while reset is held loads d, so q is not 0 during reset.
Clock capture overrides an asserted reset · case 03
A rising edge while reset is held loads d, so q is not 0 during reset.
Clock capture overrides an asserted reset · case 04
A rising edge while reset is held loads d, so q is not 0 during reset.
Clock capture overrides an asserted reset · case 05
A rising edge while reset is held loads d, so q is not 0 during reset.
Transition exactly one setup time before the edge flagged · case 01
Data that changes exactly setup time units before the clock edge is reported as a setup violation.
Transition exactly one setup time before the edge flagged · case 02
Data that changes exactly setup time units before the clock edge is reported as a setup violation.
Transition exactly one setup time before the edge flagged · case 03
Data that changes exactly setup time units before the clock edge is reported as a setup violation.
Transition exactly one setup time before the edge flagged · case 04
Data that changes exactly setup time units before the clock edge is reported as a setup violation.
Transition exactly one setup time before the edge flagged · case 05
Data that changes exactly setup time units before the clock edge is reported as a setup violation.
Data change at the clock edge escapes both checks · case 01
A data transition exactly at the rising edge is not reported at all.
Data change at the clock edge escapes both checks · case 02
A data transition exactly at the rising edge is not reported at all.
Data change at the clock edge escapes both checks · case 03
A data transition exactly at the rising edge is not reported at all.
Data change at the clock edge escapes both checks · case 04
A data transition exactly at the rising edge is not reported at all.
Data change at the clock edge escapes both checks · case 05
A data transition exactly at the rising edge is not reported at all.
Falling clock edges treated as capture edges · case 01
Data transitions near falling clock edges are reported as violations.
Falling clock edges treated as capture edges · case 02
Data transitions near falling clock edges are reported as violations.
Falling clock edges treated as capture edges · case 03
Data transitions near falling clock edges are reported as violations.
Falling clock edges treated as capture edges · case 04
Data transitions near falling clock edges are reported as violations.
Falling clock edges treated as capture edges · case 05
Data transitions near falling clock edges are reported as violations.
Clock assumed low before the first transition · case 01
A clock that starts high reports a phantom rising edge at its first redundant transition.
Clock assumed low before the first transition · case 02
A clock that starts high reports a phantom rising edge at its first redundant transition.
Clock assumed low before the first transition · case 03
A clock that starts high reports a phantom rising edge at its first redundant transition.
Clock assumed low before the first transition · case 04
A clock that starts high reports a phantom rising edge at its first redundant transition.
Clock assumed low before the first transition · case 05
A clock that starts high reports a phantom rising edge at its first redundant transition.
Violations listed by data transition instead of by edge · case 01
When windows of adjacent edges overlap, violations come out grouped by data time rather than by edge.
Violations listed by data transition instead of by edge · case 02
When windows of adjacent edges overlap, violations come out grouped by data time rather than by edge.
Violations listed by data transition instead of by edge · case 03
When windows of adjacent edges overlap, violations come out grouped by data time rather than by edge.
Violations listed by data transition instead of by edge · case 04
When windows of adjacent edges overlap, violations come out grouped by data time rather than by edge.
Violations listed by data transition instead of by edge · case 05
When windows of adjacent edges overlap, violations come out grouped by data time rather than by edge.
Arrival time taken from the earliest fanin · case 01
Reported slack is optimistic and the critical path follows a short branch.
Arrival time taken from the earliest fanin · case 02
Reported slack is optimistic and the critical path follows a short branch.
Arrival time taken from the earliest fanin · case 03
Reported slack is optimistic and the critical path follows a short branch.
Arrival time taken from the earliest fanin · case 04
Reported slack is optimistic and the critical path follows a short branch.
Arrival time taken from the earliest fanin · case 05
Reported slack is optimistic and the critical path follows a short branch.
Setup time ignored at timing endpoints · case 01
Every endpoint slack is too large by exactly the setup time.
Setup time ignored at timing endpoints · case 02
Every endpoint slack is too large by exactly the setup time.
Setup time ignored at timing endpoints · case 03
Every endpoint slack is too large by exactly the setup time.
Setup time ignored at timing endpoints · case 04
Every endpoint slack is too large by exactly the setup time.
Setup time ignored at timing endpoints · case 05
Every endpoint slack is too large by exactly the setup time.
Required time subtracts the driver delay instead of the fanout delay · case 01
Slack of internal gates is wrong whenever a gate and its fanout have different delays.
Required time subtracts the driver delay instead of the fanout delay · case 02
Slack of internal gates is wrong whenever a gate and its fanout have different delays.
Required time subtracts the driver delay instead of the fanout delay · case 03
Slack of internal gates is wrong whenever a gate and its fanout have different delays.
Required time subtracts the driver delay instead of the fanout delay · case 04
Slack of internal gates is wrong whenever a gate and its fanout have different delays.
Required time subtracts the driver delay instead of the fanout delay · case 05
Slack of internal gates is wrong whenever a gate and its fanout have different delays.
Required time keeps the loosest fanout constraint · case 01
A gate driving a slow and a fast branch is reported with the slack of the fast branch.
Required time keeps the loosest fanout constraint · case 02
A gate driving a slow and a fast branch is reported with the slack of the fast branch.
Required time keeps the loosest fanout constraint · case 03
A gate driving a slow and a fast branch is reported with the slack of the fast branch.
Required time keeps the loosest fanout constraint · case 04
A gate driving a slow and a fast branch is reported with the slack of the fast branch.
Required time keeps the loosest fanout constraint · case 05
A gate driving a slow and a fast branch is reported with the slack of the fast branch.
Critical path follows the first fanin · case 01
The reported critical path passes through a fanin that does not determine the arrival time.
Critical path follows the first fanin · case 02
The reported critical path passes through a fanin that does not determine the arrival time.
Critical path follows the first fanin · case 03
The reported critical path passes through a fanin that does not determine the arrival time.
Critical path follows the first fanin · case 04
The reported critical path passes through a fanin that does not determine the arrival time.
Critical path follows the first fanin · case 05
The reported critical path passes through a fanin that does not determine the arrival time.
Stuck-at faults on primary inputs never injected · case 01
Faults on primary inputs are reported as undetected by every vector.
Stuck-at faults on primary inputs never injected · case 02
Faults on primary inputs are reported as undetected by every vector.
Stuck-at faults on primary inputs never injected · case 03
Faults on primary inputs are reported as undetected by every vector.
Stuck-at faults on primary inputs never injected · case 04
Faults on primary inputs are reported as undetected by every vector.
Stuck-at faults on primary inputs never injected · case 05
Faults on primary inputs are reported as undetected by every vector.
Fanout branch fault applied to every reader of the stem · case 01
A branch fault is detected by vectors that only propagate through other fanout branches.
Fanout branch fault applied to every reader of the stem · case 02
A branch fault is detected by vectors that only propagate through other fanout branches.
Fanout branch fault applied to every reader of the stem · case 03
A branch fault is detected by vectors that only propagate through other fanout branches.
Fanout branch fault applied to every reader of the stem · case 04
A branch fault is detected by vectors that only propagate through other fanout branches.
Fanout branch fault applied to every reader of the stem · case 05
A branch fault is detected by vectors that only propagate through other fanout branches.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗