FA-88943 / Digital logic simulation / Member archive

Transition exactly one setup time before the edge flagged · case 03

Data that changes exactly setup time units before the clock edge is reported as a setup violation.

Member previewVariant 3 · 3 implementations · 7 checks per implementation

Case contract

Input [c0, clock, data, setup, hold]: c0 is the initial clock level, clock is time-sorted [t, v] transitions (possibly redundant), data is a list of data transition times. Rising edges are 0->1 changes only. For every data time t and every rising edge e: e-setup < t < e is a 'setup' violation, e <= t < e+hold is a 'hold' violation. Return all [e, t, kind] sorted by edge, then time.

Why this case matters

Timing checks in gate-level simulation decide which transitions corrupt a register; window boundaries and edge extraction are the classic bug sites.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
setup window boundaries	`[[10, 7, "setup"], [10, 8, "setup"], [20, 17, "setup"], [30, 27, "setup"]]`	`[[10, 8, "setup"]]`	Failed

MEMBER ARCHIVE

The complete case is available to members.

This record includes three runnable implementations, regression fixtures, execution results, and source hashes.

Member access is invitation-based. Sign in with your invited account to inspect the sources.