FA-88939 / Digital logic simulation / Member archive
Clock capture overrides an asserted reset · case 04
A rising edge while reset is held loads d, so q is not 0 during reset.
Case contract
Input: samples [clk, d, en, rst_n] at successive instants. q starts as "x". Active-low rst_n==0 forces q=0 immediately regardless of clock. Otherwise a rising clock edge (previous sample clk 0, this sample clk 1; the first sample is never an edge) with en==1 loads d. The previous clock value is tracked on every sample, including while reset is asserted. Return q after each sample.
Why this case matters
Register models in cycle simulators must distinguish asynchronous from synchronous control and detect true clock edges.
One recorded failure
Sample boundary fixtureThis sample comes from the broken implementation of a controlled reproducer.
| Boundary fixture | Actual | Expected | Outcome |
|---|---|---|---|
| reset held low while clock rises | [0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1] | [0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1] | Failed |
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