Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Valence is taken from incident face count plus one · case 01
Interior vertices of closed meshes are over-counted by one each.
Valence is taken from incident face count plus one · case 02
Interior vertices of closed meshes are over-counted by one each.
Valence is taken from incident face count plus one · case 03
Interior vertices of closed meshes are over-counted by one each.
Valence is taken from incident face count plus one · case 04
Interior vertices of closed meshes are over-counted by one each.
Valence is taken from incident face count plus one · case 05
Interior vertices of closed meshes are over-counted by one each.
Triangle boundary vertices are held to the interior valence · case 01
Open triangle meshes fail the index identity.
Triangle boundary vertices are held to the interior valence · case 02
Open triangle meshes fail the index identity.
Triangle boundary vertices are held to the interior valence · case 03
Open triangle meshes fail the index identity.
Triangle boundary vertices are held to the interior valence · case 04
Open triangle meshes fail the index identity.
Triangle boundary vertices are held to the interior valence · case 05
Open triangle meshes fail the index identity.
Index identity derives the edge count from corner uses · case 01
Open meshes get a wrong Euler characteristic, so the index identity fails.
Index identity derives the edge count from corner uses · case 02
Open meshes get a wrong Euler characteristic, so the index identity fails.
Index identity derives the edge count from corner uses · case 03
Open meshes get a wrong Euler characteristic, so the index identity fails.
Index identity derives the edge count from corner uses · case 04
Open meshes get a wrong Euler characteristic, so the index identity fails.
Index identity derives the edge count from corner uses · case 05
Open meshes get a wrong Euler characteristic, so the index identity fails.
Index identity uses the triangle multiplier for every mesh kind · case 01
Quad meshes report a failed identity.
Index identity uses the triangle multiplier for every mesh kind · case 02
Quad meshes report a failed identity.
Index identity uses the triangle multiplier for every mesh kind · case 03
Quad meshes report a failed identity.
Index identity uses the triangle multiplier for every mesh kind · case 04
Quad meshes report a failed identity.
Index identity uses the triangle multiplier for every mesh kind · case 05
Quad meshes report a failed identity.
Face adjacency counts a neighbour once per shared edge · case 01
Faces sharing two edges report degree 2 for one neighbour.
Face adjacency counts a neighbour once per shared edge · case 02
Faces sharing two edges report degree 2 for one neighbour.
Face adjacency counts a neighbour once per shared edge · case 03
Faces sharing two edges report degree 2 for one neighbour.
Face adjacency counts a neighbour once per shared edge · case 04
Faces sharing two edges report degree 2 for one neighbour.
Face adjacency counts a neighbour once per shared edge · case 05
Faces sharing two edges report degree 2 for one neighbour.
Face is counted as its own neighbour · case 01
Every face degree is one too high.
Face is counted as its own neighbour · case 02
Every face degree is one too high.
Face is counted as its own neighbour · case 03
Every face degree is one too high.
Face is counted as its own neighbour · case 04
Every face degree is one too high.
Face is counted as its own neighbour · case 05
Every face degree is one too high.
Face adjacency is keyed by directed edges · case 01
Consistently oriented neighbours are not found; only flipped ones are.
Face adjacency is keyed by directed edges · case 02
Consistently oriented neighbours are not found; only flipped ones are.
Face adjacency is keyed by directed edges · case 03
Consistently oriented neighbours are not found; only flipped ones are.
Face adjacency is keyed by directed edges · case 04
Consistently oriented neighbours are not found; only flipped ones are.
Face adjacency is keyed by directed edges · case 05
Consistently oriented neighbours are not found; only flipped ones are.
Adjacent pair count uses interior edges · case 01
Face pairs sharing two edges or fins are miscounted.
Adjacent pair count uses interior edges · case 02
Face pairs sharing two edges or fins are miscounted.
Adjacent pair count uses interior edges · case 03
Face pairs sharing two edges or fins are miscounted.
Adjacent pair count uses interior edges · case 04
Face pairs sharing two edges or fins are miscounted.
Adjacent pair count uses interior edges · case 05
Face pairs sharing two edges or fins are miscounted.
Unknown input overrides a controlling zero on an AND gate · case 01
An AND gate with a 0 input and an unknown input reports x instead of the definite 0.
Unknown input overrides a controlling zero on an AND gate · case 02
An AND gate with a 0 input and an unknown input reports x instead of the definite 0.
Unknown input overrides a controlling zero on an AND gate · case 03
An AND gate with a 0 input and an unknown input reports x instead of the definite 0.
Unknown input overrides a controlling zero on an AND gate · case 04
An AND gate with a 0 input and an unknown input reports x instead of the definite 0.
Unknown input overrides a controlling zero on an AND gate · case 05
An AND gate with a 0 input and an unknown input reports x instead of the definite 0.
Floating gate input is evaluated as a literal z · case 01
A buffer driven by a floating net outputs 'z' and an XOR with a floating pin produces a definite parity.
Floating gate input is evaluated as a literal z · case 02
A buffer driven by a floating net outputs 'z' and an XOR with a floating pin produces a definite parity.
Floating gate input is evaluated as a literal z · case 03
A buffer driven by a floating net outputs 'z' and an XOR with a floating pin produces a definite parity.
Floating gate input is evaluated as a literal z · case 04
A buffer driven by a floating net outputs 'z' and an XOR with a floating pin produces a definite parity.
Floating gate input is evaluated as a literal z · case 05
A buffer driven by a floating net outputs 'z' and an XOR with a floating pin produces a definite parity.
XOR parity ignores unknown inputs · case 01
An XOR gate with an unknown input returns a definite parity bit.
XOR parity ignores unknown inputs · case 02
An XOR gate with an unknown input returns a definite parity bit.
XOR parity ignores unknown inputs · case 03
An XOR gate with an unknown input returns a definite parity bit.
XOR parity ignores unknown inputs · case 04
An XOR gate with an unknown input returns a definite parity bit.
XOR parity ignores unknown inputs · case 05
An XOR gate with an unknown input returns a definite parity bit.
XNOR output is not inverted · case 01
An XNOR gate returns the same value as XOR.
XNOR output is not inverted · case 02
An XNOR gate returns the same value as XOR.
XNOR output is not inverted · case 03
An XNOR gate returns the same value as XOR.
XNOR output is not inverted · case 04
An XNOR gate returns the same value as XOR.
XNOR output is not inverted · case 05
An XNOR gate returns the same value as XOR.
Unknown enable on a tri-state buffer releases the net · case 01
A bufif1 with an unknown enable drives 'z' instead of an unknown value.
Unknown enable on a tri-state buffer releases the net · case 02
A bufif1 with an unknown enable drives 'z' instead of an unknown value.
Unknown enable on a tri-state buffer releases the net · case 03
A bufif1 with an unknown enable drives 'z' instead of an unknown value.
Unknown enable on a tri-state buffer releases the net · case 04
A bufif1 with an unknown enable drives 'z' instead of an unknown value.
Unknown enable on a tri-state buffer releases the net · case 05
A bufif1 with an unknown enable drives 'z' instead of an unknown value.
Gate delay behaves as transport delay · case 01
A pulse narrower than the gate delay appears on the output instead of being swallowed.
Gate delay behaves as transport delay · case 02
A pulse narrower than the gate delay appears on the output instead of being swallowed.
Gate delay behaves as transport delay · case 03
A pulse narrower than the gate delay appears on the output instead of being swallowed.
Gate delay behaves as transport delay · case 04
A pulse narrower than the gate delay appears on the output instead of being swallowed.
Gate delay behaves as transport delay · case 05
A pulse narrower than the gate delay appears on the output instead of being swallowed.
Rise or fall delay chosen from the input edge · case 01
An inverter output falls after the rise delay and rises after the fall delay.
Rise or fall delay chosen from the input edge · case 02
An inverter output falls after the rise delay and rises after the fall delay.
Rise or fall delay chosen from the input edge · case 03
An inverter output falls after the rise delay and rises after the fall delay.
Rise or fall delay chosen from the input edge · case 04
An inverter output falls after the rise delay and rises after the fall delay.
Rise or fall delay chosen from the input edge · case 05
An inverter output falls after the rise delay and rises after the fall delay.
Redundant output events are reported as edges · case 01
The waveform lists a transition to the value the output already holds.
Redundant output events are reported as edges · case 02
The waveform lists a transition to the value the output already holds.
Redundant output events are reported as edges · case 03
The waveform lists a transition to the value the output already holds.
Redundant output events are reported as edges · case 04
The waveform lists a transition to the value the output already holds.
Redundant output events are reported as edges · case 05
The waveform lists a transition to the value the output already holds.
Initial output ignores the gate function · case 01
An inverter whose input starts low is assumed to start low, so its first falling edge disappears.
Initial output ignores the gate function · case 02
An inverter whose input starts low is assumed to start low, so its first falling edge disappears.
Initial output ignores the gate function · case 03
An inverter whose input starts low is assumed to start low, so its first falling edge disappears.
Initial output ignores the gate function · case 04
An inverter whose input starts low is assumed to start low, so its first falling edge disappears.
Initial output ignores the gate function · case 05
An inverter whose input starts low is assumed to start low, so its first falling edge disappears.
Output events pending after the last stimulus are lost · case 01
The final output transition is missing whenever it matures after the last input change.
Output events pending after the last stimulus are lost · case 02
The final output transition is missing whenever it matures after the last input change.
Output events pending after the last stimulus are lost · case 03
The final output transition is missing whenever it matures after the last input change.
Output events pending after the last stimulus are lost · case 04
The final output transition is missing whenever it matures after the last input change.
Output events pending after the last stimulus are lost · case 05
The final output transition is missing whenever it matures after the last input change.
Gate level taken from the shallowest fanin · case 01
Reconvergent logic reports a smaller depth than its longest path.
Gate level taken from the shallowest fanin · case 02
Reconvergent logic reports a smaller depth than its longest path.
Gate level taken from the shallowest fanin · case 03
Reconvergent logic reports a smaller depth than its longest path.
Gate level taken from the shallowest fanin · case 04
Reconvergent logic reports a smaller depth than its longest path.
Gate level taken from the shallowest fanin · case 05
Reconvergent logic reports a smaller depth than its longest path.
Constant tie cells counted as a logic level · case 01
A chain fed by a tie cell reports one extra level of depth.
Constant tie cells counted as a logic level · case 02
A chain fed by a tie cell reports one extra level of depth.
Constant tie cells counted as a logic level · case 03
A chain fed by a tie cell reports one extra level of depth.
Constant tie cells counted as a logic level · case 04
A chain fed by a tie cell reports one extra level of depth.
Constant tie cells counted as a logic level · case 05
A chain fed by a tie cell reports one extra level of depth.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗