FA-88875 / Digital logic simulation / Member archive

Rise or fall delay chosen from the input edge · case 05

An inverter output falls after the rise delay and rises after the fall delay.

Member previewVariant 5 · 3 implementations · 7 checks per implementation

Case contract

Input [gate, rise_delay, fall_delay, v0, events]; gate is 'buf' or 'not', events are time-sorted [t, v] input changes. Output starts at f(v0) (not reported). Each input change schedules f(v) at t + rise_delay when f(v)==1 else t + fall_delay, and cancels every pending output event (inertial delay). Pending events maturing at or before the next input time are committed first. Report [time, value] only when the output value changes; all pending events are committed after the last input.

Why this case matters

Event-driven simulators filter pulses narrower than a gate delay; getting cancellation, polarity and flushing right determines the waveform.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
inverter uses output polarity for delay	`[[12, 0], [40, 1]]`	`[[20, 0], [32, 1]]`	Failed

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