FA-88892 / Digital logic simulation / Member archive

Gate level taken from the shallowest fanin · case 02

Reconvergent logic reports a smaller depth than its longest path.

Member previewVariant 2 · 3 implementations · 8 checks per implementation

Case contract

Input [pis, gates]: pis maps primary input net -> 0/1; gates are [out, op, ins] in any order with ops and/or/xor/nand/not/tie0/tie1. Reject with 'undriven <net>' (first gate in list order, first pin) if a gate reads a net driven by nobody, or 'multiply driven <net>' if a net has two drivers (a gate driving a primary input counts). Otherwise evaluate in dependency waves; return 'loop' if no gate becomes ready. Level: primary inputs 0, gate = 1 + max input level, tie cells 0. Return {'depth': max level, 'values': sorted [net, value]}.

Why this case matters

Levelized compiled-code simulators must order gates by dependency and diagnose structural netlist errors before evaluating.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
reconvergent netlist listed out of order	`{"depth": 1, "values": [["a", 0], ["b", 1], ["c", 1], ["g1", 1], ["g2", 1], ["g3", 1], ["g4", 1]]}`	`{"depth": 3, "values": [["a", 0], ["b", 1], ["c", 1], ["g1", 1], ["g2", 1], ["g3", 1], ["g4", 1]]}`	Failed

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