FA-88848 / Digital logic simulation / Member archive

Floating gate input is evaluated as a literal z · case 03

A buffer driven by a floating net outputs 'z' and an XOR with a floating pin produces a definite parity.

Member previewVariant 3 · 3 implementations · 11 checks per implementation

Case contract

Values are '0','1','x','z'. A 'z' on any gate input is read as 'x'. and/nand: any 0 -> 0, all 1 -> 1, else x; or/nor: any 1 -> 1, all 0 -> 0, else x; xor/xnor: any x -> x, else parity of ones; buf/not use the single input; nand/nor/xnor/not invert (x stays x). bufif1(data, enable): enable 0 -> 'z', enable x/z -> 'x', enable 1 -> data (z data becomes x).

Why this case matters

Gate-level logic simulators must propagate unknown and high-impedance values without inventing definite levels.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
xor gate: floating input	`"1"`	`"x"`	Failed

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