FA-88950 / Digital logic simulation / Member archive

Data change at the clock edge escapes both checks · case 05

A data transition exactly at the rising edge is not reported at all.

Member previewVariant 5 · 3 implementations · 7 checks per implementation

Case contract

Input [c0, clock, data, setup, hold]: c0 is the initial clock level, clock is time-sorted [t, v] transitions (possibly redundant), data is a list of data transition times. Rising edges are 0->1 changes only. For every data time t and every rising edge e: e-setup < t < e is a 'setup' violation, e <= t < e+hold is a 'hold' violation. Return all [e, t, kind] sorted by edge, then time.

Why this case matters

Timing checks in gate-level simulation decide which transitions corrupt a register; window boundaries and edge extraction are the classic bug sites.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
transition exactly at the clock edge	`[[30, 29, "setup"]]`	`[[20, 20, "hold"], [30, 29, "setup"]]`	Failed

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