FA-89198 / Digital logic simulation / Member archive

Forbidden SR input resolved as reset · case 03

S=R=1 produces a definite 0 instead of 'x'.

Member previewVariant 3 · 3 implementations · 7 checks per implementation

Case contract

Input [kind, q0, ins] with one [a, b] pair per clock edge. jk (a=J, b=K): 00 hold, 10 set, 01 reset, 11 toggle. sr (a=S, b=R): 10 set, 01 reset, 00 hold, 11 is forbidden and makes q 'x'. t (a=T): 1 toggles, 0 holds, 'x' makes q 'x'. Toggling 'x' gives 'x'. Return q after each edge.

Why this case matters

Behavioural flip-flop primitives in gate-level libraries must reproduce characteristic tables, including unknown handling.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
sr forbidden input	`[1, 0, 0, 0, 1, 1, 1]`	`[1, "x", "x", 0, 1, 1, 1]`	Failed

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