FA-89124 / Digital logic simulation / Member archive

Any byte enable writes the whole word · case 04

A single-lane write clobbers the other byte lane.

Member previewVariant 4 · 3 implementations · 7 checks per implementation

Case contract

Input [depth, mode, ops]; memory holds 16-bit words initialised to 0. Each op [we, addr, wdata, be, re]: be bit k enables byte lane k (bits 8k..8k+7). Addresses outside 0..depth-1 ignore writes and read 'x'. A read in the same cycle as a write returns the old word in mode 'read_first' and the merged new word in 'write_first'. re=0 yields None.

Why this case matters

RTL memory models must match the inferred RAM read-during-write and byte-enable behaviour or simulation diverges from silicon.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
write-first partial write	`[null, 65535, 65535]`	`[null, 4863, 4863]`	Failed

MEMBER ARCHIVE

The complete case is available to members.

This record includes three runnable implementations, regression fixtures, execution results, and source hashes.

Member access is invitation-based. Sign in with your invited account to inspect the sources.