FA-89294 / Digital logic simulation / Member archive

Gated clock uses the raw enable · case 04

Changing enable while the clock is high chops or creates clock pulses.

Member previewVariant 4 · 3 implementations · 6 checks per implementation

Case contract

Input [samples] of [clk, en, te]. The enable latch starts at 0 and is transparent while clk is 0 (q = en or te), holding while clk is 1. The gated clock is clk and q. Return [gated clock per sample, number of gated rising edges counting from an initial low].

Why this case matters

Integrated clock gating cells rely on a low-transparent latch to avoid glitches; simulation models that skip the latch show clock pulses that silicon never produces.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
enable drops while clock high	`[[0, 1, 0, 0, 0], 1]`	`[[0, 1, 1, 0, 0], 1]`	Failed

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