Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Branch target computed from the branch address · case 01
Taken branches land one instruction early.
Branch target computed from the branch address · case 02
Taken branches land one instruction early.
Branch target computed from the branch address · case 03
Taken branches land one instruction early.
Branch target computed from the branch address · case 04
Taken branches land one instruction early.
Branch target computed from the branch address · case 05
Taken branches land one instruction early.
Delay slot skipped on taken branches · case 01
The instruction after a taken branch never executes.
Delay slot skipped on taken branches · case 02
The instruction after a taken branch never executes.
Delay slot skipped on taken branches · case 03
The instruction after a taken branch never executes.
Delay slot skipped on taken branches · case 04
The instruction after a taken branch never executes.
Delay slot skipped on taken branches · case 05
The instruction after a taken branch never executes.
Branch-likely delay slot not annulled · case 01
The delay slot of a not-taken branch-likely instruction still executes.
Branch-likely delay slot not annulled · case 02
The delay slot of a not-taken branch-likely instruction still executes.
Branch-likely delay slot not annulled · case 03
The delay slot of a not-taken branch-likely instruction still executes.
Branch-likely delay slot not annulled · case 04
The delay slot of a not-taken branch-likely instruction still executes.
Branch-likely delay slot not annulled · case 05
The delay slot of a not-taken branch-likely instruction still executes.
Backward branch offset not sign-extended · case 01
A backward loop branch jumps far forward out of the program.
Backward branch offset not sign-extended · case 02
A backward loop branch jumps far forward out of the program.
Backward branch offset not sign-extended · case 03
A backward loop branch jumps far forward out of the program.
Backward branch offset not sign-extended · case 04
A backward loop branch jumps far forward out of the program.
Backward branch offset not sign-extended · case 05
A backward loop branch jumps far forward out of the program.
Writes to r0 are kept · case 01
After addi r0, r0 is nonzero and later reads of r0 are wrong.
Writes to r0 are kept · case 02
After addi r0, r0 is nonzero and later reads of r0 are wrong.
Writes to r0 are kept · case 03
After addi r0, r0 is nonzero and later reads of r0 are wrong.
Writes to r0 are kept · case 04
After addi r0, r0 is nonzero and later reads of r0 are wrong.
Writes to r0 are kept · case 05
After addi r0, r0 is nonzero and later reads of r0 are wrong.
Privilege requirement read from the access-type bits · case 01
Supervisor code can access machine CSRs.
Privilege requirement read from the access-type bits · case 02
Supervisor code can access machine CSRs.
Privilege requirement read from the access-type bits · case 03
Supervisor code can access machine CSRs.
Privilege requirement read from the access-type bits · case 04
Supervisor code can access machine CSRs.
Privilege requirement read from the access-type bits · case 05
Supervisor code can access machine CSRs.
Writable CSR range treated as read-only · case 01
Writes to CSRs whose top bits are 10 trap as illegal.
Writable CSR range treated as read-only · case 02
Writes to CSRs whose top bits are 10 trap as illegal.
Writable CSR range treated as read-only · case 03
Writes to CSRs whose top bits are 10 trap as illegal.
Writable CSR range treated as read-only · case 04
Writes to CSRs whose top bits are 10 trap as illegal.
Writable CSR range treated as read-only · case 05
Writes to CSRs whose top bits are 10 trap as illegal.
Write intent derived from the register value · case 01
csrrs with rs1=x0 on a read-only counter traps, and a set with a zero-valued nonzero register does not.
Write intent derived from the register value · case 02
csrrs with rs1=x0 on a read-only counter traps, and a set with a zero-valued nonzero register does not.
Write intent derived from the register value · case 03
csrrs with rs1=x0 on a read-only counter traps, and a set with a zero-valued nonzero register does not.
Write intent derived from the register value · case 04
csrrs with rs1=x0 on a read-only counter traps, and a set with a zero-valued nonzero register does not.
Write intent derived from the register value · case 05
csrrs with rs1=x0 on a read-only counter traps, and a set with a zero-valued nonzero register does not.
csrrwi with zero immediate treated as a read · case 01
An immediate write of 0 to a read-only CSR does not trap.
csrrwi with zero immediate treated as a read · case 02
An immediate write of 0 to a read-only CSR does not trap.
csrrwi with zero immediate treated as a read · case 03
An immediate write of 0 to a read-only CSR does not trap.
csrrwi with zero immediate treated as a read · case 04
An immediate write of 0 to a read-only CSR does not trap.
csrrwi with zero immediate treated as a read · case 05
An immediate write of 0 to a read-only CSR does not trap.
CSR clear-bits toggles bits · case 01
csrrc sets bits that were clear in the CSR.
CSR clear-bits toggles bits · case 02
csrrc sets bits that were clear in the CSR.
CSR clear-bits toggles bits · case 03
csrrc sets bits that were clear in the CSR.
CSR clear-bits toggles bits · case 04
csrrc sets bits that were clear in the CSR.
CSR clear-bits toggles bits · case 05
csrrc sets bits that were clear in the CSR.
Immediate CSR forms use the register value · case 01
csrrsi sets the bits of an unrelated register value instead of the 5-bit immediate.
Immediate CSR forms use the register value · case 02
csrrsi sets the bits of an unrelated register value instead of the 5-bit immediate.
Immediate CSR forms use the register value · case 03
csrrsi sets the bits of an unrelated register value instead of the 5-bit immediate.
Immediate CSR forms use the register value · case 04
csrrsi sets the bits of an unrelated register value instead of the 5-bit immediate.
Immediate CSR forms use the register value · case 05
csrrsi sets the bits of an unrelated register value instead of the 5-bit immediate.
Every ecall reported as a machine-mode call · case 01
User and supervisor system calls carry the machine-mode cause code.
Every ecall reported as a machine-mode call · case 02
User and supervisor system calls carry the machine-mode cause code.
Every ecall reported as a machine-mode call · case 03
User and supervisor system calls carry the machine-mode cause code.
Every ecall reported as a machine-mode call · case 04
User and supervisor system calls carry the machine-mode cause code.
Every ecall reported as a machine-mode call · case 05
User and supervisor system calls carry the machine-mode cause code.
Machine interrupts masked in lower privilege modes · case 01
An interrupt arriving in supervisor mode with MIE clear is ignored.
Machine interrupts masked in lower privilege modes · case 02
An interrupt arriving in supervisor mode with MIE clear is ignored.
Machine interrupts masked in lower privilege modes · case 03
An interrupt arriving in supervisor mode with MIE clear is ignored.
Machine interrupts masked in lower privilege modes · case 04
An interrupt arriving in supervisor mode with MIE clear is ignored.
Machine interrupts masked in lower privilege modes · case 05
An interrupt arriving in supervisor mode with MIE clear is ignored.
MPIE captures the already cleared enable · case 01
After mret interrupts stay disabled even though they were enabled before the trap.
MPIE captures the already cleared enable · case 02
After mret interrupts stay disabled even though they were enabled before the trap.
MPIE captures the already cleared enable · case 03
After mret interrupts stay disabled even though they were enabled before the trap.
MPIE captures the already cleared enable · case 04
After mret interrupts stay disabled even though they were enabled before the trap.
MPIE captures the already cleared enable · case 05
After mret interrupts stay disabled even though they were enabled before the trap.
Exceptions dispatched through the interrupt vector table · case 01
In vectored mode an illegal instruction jumps to base + 8 instead of base.
Exceptions dispatched through the interrupt vector table · case 02
In vectored mode an illegal instruction jumps to base + 8 instead of base.
Exceptions dispatched through the interrupt vector table · case 03
In vectored mode an illegal instruction jumps to base + 8 instead of base.
Exceptions dispatched through the interrupt vector table · case 04
In vectored mode an illegal instruction jumps to base + 8 instead of base.
Exceptions dispatched through the interrupt vector table · case 05
In vectored mode an illegal instruction jumps to base + 8 instead of base.
Trap vector includes the mode bits · case 01
With vectored mode enabled, traps jump to an odd address.
Trap vector includes the mode bits · case 02
With vectored mode enabled, traps jump to an odd address.
Trap vector includes the mode bits · case 03
With vectored mode enabled, traps jump to an odd address.
Trap vector includes the mode bits · case 04
With vectored mode enabled, traps jump to an odd address.
Trap vector includes the mode bits · case 05
With vectored mode enabled, traps jump to an odd address.
MPP not cleared by mret · case 01
A second mret without an intervening trap returns to the old privilege instead of user mode.
MPP not cleared by mret · case 02
A second mret without an intervening trap returns to the old privilege instead of user mode.
MPP not cleared by mret · case 03
A second mret without an intervening trap returns to the old privilege instead of user mode.
MPP not cleared by mret · case 04
A second mret without an intervening trap returns to the old privilege instead of user mode.
MPP not cleared by mret · case 05
A second mret without an intervening trap returns to the old privilege instead of user mode.
Rotate left is circular instead of through carry · case 01
rol feeds bit 7 back into bit 0 instead of the carry flag.
Rotate left is circular instead of through carry · case 02
rol feeds bit 7 back into bit 0 instead of the carry flag.
Rotate left is circular instead of through carry · case 03
rol feeds bit 7 back into bit 0 instead of the carry flag.
Rotate left is circular instead of through carry · case 04
rol feeds bit 7 back into bit 0 instead of the carry flag.
Rotate left is circular instead of through carry · case 05
rol feeds bit 7 back into bit 0 instead of the carry flag.
Rotate right is circular instead of through carry · case 01
ror moves bit 0 into bit 7 rather than the old carry.
Rotate right is circular instead of through carry · case 02
ror moves bit 0 into bit 7 rather than the old carry.
Rotate right is circular instead of through carry · case 03
ror moves bit 0 into bit 7 rather than the old carry.
Rotate right is circular instead of through carry · case 04
ror moves bit 0 into bit 7 rather than the old carry.
Rotate right is circular instead of through carry · case 05
ror moves bit 0 into bit 7 rather than the old carry.
Rotate uses the new carry as its input bit · case 01
rol shifts the outgoing bit 7 back in because carry is updated first.
Rotate uses the new carry as its input bit · case 02
rol shifts the outgoing bit 7 back in because carry is updated first.
Rotate uses the new carry as its input bit · case 03
rol shifts the outgoing bit 7 back in because carry is updated first.
Rotate uses the new carry as its input bit · case 04
rol shifts the outgoing bit 7 back in because carry is updated first.
Rotate uses the new carry as its input bit · case 05
rol shifts the outgoing bit 7 back in because carry is updated first.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗