FAILURE MAP
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FA-89796 / Instruction set emulation / Open access

Rotate uses the new carry as its input bit · case 01

rol shifts the outgoing bit 7 back in because carry is updated first.

Verified by executionVariant 1 · 8 checks per implementationDownload source bundle ↓JSON ↗

ROOT CAUSE

Carry is overwritten before the rotated value is computed.

VERIFIED REPAIR

Compute the new value from the old carry, then update carry from the old value.

Unsuccessful approach: Computing carry after the shift reads bit 7 of the new value.

Case contract

Input [a, c, ops] with ops asl, lsr, rol, ror, asr on an 8-bit value and a carry bit. asl: C = bit 7, shift left. lsr: C = bit 0, shift right with 0. rol: shift left, bit 0 = old C, new C = old bit 7. ror: shift right, bit 7 = old C, new C = old bit 0. asr: C = bit 0, shift right keeping bit 7. Report [A, C, Z, N] after each op.

Why this case matters

Rotate-through-carry instructions implement multi-byte shifts in 8-bit code; emulating them with circular rotates or sequenced updates breaks arithmetic libraries.

1 / The failure

Exit 1
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    a, c, ops = args
    out = []
    for op in ops:
        if op == 'asl':
            c = a >> 7
            a = (a << 1) & 0xFF
        elif op == 'lsr':
            c = a & 1
            a = a >> 1
        elif op == 'rol':
            c = a >> 7
            a = ((a << 1) | c) & 0xFF
        elif op == 'ror':
            a, c = (a >> 1) | (c << 7), a & 1
        elif op == 'asr':
            c = a & 1
            a = (a >> 1) | (a & 0x80)
        out.append([a, c, int(a == 0), a >> 7])
    return out
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]), ('rotate left with carry in', [65, 1, ['rol', 'rol']], [[131, 0, 0, 1], [6, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [4, 1, ['ror', 'ror']], [[130, 0, 0, 1], [65, 0, 0, 0]]), ('arithmetic right shift keeps sign', [197, 0, ['asr', 'asr', 'asr']], [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [5, 0, ['lsr', 'lsr']], [[2, 1, 0, 0], [1, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [86, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0]]), ('rotate left with carry in', [66, 1, ['rol', 'rol']], [[133, 0, 0, 1], [10, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [6, 1, ['ror', 'ror']], [[131, 0, 0, 1], [65, 1, 0, 0]]), ('arithmetic right shift keeps sign', [198, 0, ['asr', 'asr', 'asr']], [[227, 0, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [9, 0, ['lsr', 'lsr']], [[4, 1, 0, 0], [2, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [87, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[175, 0, 0, 1], [87, 1, 0, 0], [171, 1, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0]]), ('rotate left with carry in', [67, 1, ['rol', 'rol']], [[135, 0, 0, 1], [14, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [8, 1, ['ror', 'ror']], [[132, 0, 0, 1], [66, 0, 0, 0]]), ('arithmetic right shift keeps sign', [199, 0, ['asr', 'asr', 'asr']], [[227, 1, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [13, 0, ['lsr', 'lsr']], [[6, 1, 0, 0], [3, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [88, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[177, 0, 0, 1], [88, 1, 0, 0], [172, 0, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1]]), ('rotate left with carry in', [68, 1, ['rol', 'rol']], [[137, 0, 0, 1], [18, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [10, 1, ['ror', 'ror']], [[133, 0, 0, 1], [66, 1, 0, 0]]), ('arithmetic right shift keeps sign', [200, 0, ['asr', 'asr', 'asr']], [[228, 0, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [17, 0, ['lsr', 'lsr']], [[8, 1, 0, 0], [4, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [89, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[179, 0, 0, 1], [89, 1, 0, 0], [172, 1, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1], [64, 1, 0, 0]]), ('rotate left with carry in', [69, 1, ['rol', 'rol']], [[139, 0, 0, 1], [22, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [12, 1, ['ror', 'ror']], [[134, 0, 0, 1], [67, 0, 0, 0]]), ('arithmetic right shift keeps sign', [201, 0, ['asr', 'asr', 'asr']], [[228, 1, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [21, 0, ['lsr', 'lsr']], [[10, 1, 0, 0], [5, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [90, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[181, 0, 0, 1], [90, 1, 0, 0], [173, 0, 0, 1], [214, 1, 0, 1], [172, 1, 0, 1]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
rotate left through carry[[3, 1, 0, 0], [6, 0, 0, 0], [12, 0, 0, 0], [24, 0, 0, 0]][[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]Failed
rotate left with carry in[[130, 0, 0, 1], [5, 1, 0, 0]][[131, 0, 0, 1], [6, 1, 0, 0]]Failed
rotate right through carry[[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]][[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]Passed
rotate right carry into bit seven[[130, 0, 0, 1], [65, 0, 0, 0]][[130, 0, 0, 1], [65, 0, 0, 0]]Passed
arithmetic right shift keeps sign[[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]][[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]Passed
logical right shift carry[[2, 1, 0, 0], [1, 0, 0, 0]][[2, 1, 0, 0], [1, 0, 0, 0]]Passed
shift left carry out[[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]][[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]Passed
mixed sequence[[172, 0, 0, 1], [86, 0, 0, 0], [43, 0, 0, 0], [21, 1, 0, 0], [42, 0, 0, 0]][[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]]Failed

SHA-256 / 98f564d6cf4172e885c6c4b46923b8f07d582d3e19c932e3b8d8f5bb95974812

2 / The unsuccessful fix

Exit 1
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    a, c, ops = args
    out = []
    for op in ops:
        if op == 'asl':
            c = a >> 7
            a = (a << 1) & 0xFF
        elif op == 'lsr':
            c = a & 1
            a = a >> 1
        elif op == 'rol':
            a = ((a << 1) | c) & 0xFF
            c = a >> 7
        elif op == 'ror':
            a, c = (a >> 1) | (c << 7), a & 1
        elif op == 'asr':
            c = a & 1
            a = (a >> 1) | (a & 0x80)
        out.append([a, c, int(a == 0), a >> 7])
    return out
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]), ('rotate left with carry in', [65, 1, ['rol', 'rol']], [[131, 0, 0, 1], [6, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [4, 1, ['ror', 'ror']], [[130, 0, 0, 1], [65, 0, 0, 0]]), ('arithmetic right shift keeps sign', [197, 0, ['asr', 'asr', 'asr']], [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [5, 0, ['lsr', 'lsr']], [[2, 1, 0, 0], [1, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [86, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0]]), ('rotate left with carry in', [66, 1, ['rol', 'rol']], [[133, 0, 0, 1], [10, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [6, 1, ['ror', 'ror']], [[131, 0, 0, 1], [65, 1, 0, 0]]), ('arithmetic right shift keeps sign', [198, 0, ['asr', 'asr', 'asr']], [[227, 0, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [9, 0, ['lsr', 'lsr']], [[4, 1, 0, 0], [2, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [87, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[175, 0, 0, 1], [87, 1, 0, 0], [171, 1, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0]]), ('rotate left with carry in', [67, 1, ['rol', 'rol']], [[135, 0, 0, 1], [14, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [8, 1, ['ror', 'ror']], [[132, 0, 0, 1], [66, 0, 0, 0]]), ('arithmetic right shift keeps sign', [199, 0, ['asr', 'asr', 'asr']], [[227, 1, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [13, 0, ['lsr', 'lsr']], [[6, 1, 0, 0], [3, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [88, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[177, 0, 0, 1], [88, 1, 0, 0], [172, 0, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1]]), ('rotate left with carry in', [68, 1, ['rol', 'rol']], [[137, 0, 0, 1], [18, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [10, 1, ['ror', 'ror']], [[133, 0, 0, 1], [66, 1, 0, 0]]), ('arithmetic right shift keeps sign', [200, 0, ['asr', 'asr', 'asr']], [[228, 0, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [17, 0, ['lsr', 'lsr']], [[8, 1, 0, 0], [4, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [89, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[179, 0, 0, 1], [89, 1, 0, 0], [172, 1, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1], [64, 1, 0, 0]]), ('rotate left with carry in', [69, 1, ['rol', 'rol']], [[139, 0, 0, 1], [22, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [12, 1, ['ror', 'ror']], [[134, 0, 0, 1], [67, 0, 0, 0]]), ('arithmetic right shift keeps sign', [201, 0, ['asr', 'asr', 'asr']], [[228, 1, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [21, 0, ['lsr', 'lsr']], [[10, 1, 0, 0], [5, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [90, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[181, 0, 0, 1], [90, 1, 0, 0], [173, 0, 0, 1], [214, 1, 0, 1], [172, 1, 0, 1]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
rotate left through carry[[2, 0, 0, 0], [4, 0, 0, 0], [8, 0, 0, 0], [16, 0, 0, 0]][[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]Failed
rotate left with carry in[[131, 1, 0, 1], [7, 0, 0, 0]][[131, 0, 0, 1], [6, 1, 0, 0]]Failed
rotate right through carry[[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]][[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]Passed
rotate right carry into bit seven[[130, 0, 0, 1], [65, 0, 0, 0]][[130, 0, 0, 1], [65, 0, 0, 0]]Passed
arithmetic right shift keeps sign[[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]][[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]Passed
logical right shift carry[[2, 1, 0, 0], [1, 0, 0, 0]][[2, 1, 0, 0], [1, 0, 0, 0]]Passed
shift left carry out[[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]][[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]Passed
mixed sequence[[173, 1, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]][[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]]Failed

SHA-256 / a51efba40ef99a677450212291303f5a8e580962df721310d9a4614ebaaab00d

3 / The verified repair

Exit 0
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    a, c, ops = args
    out = []
    for op in ops:
        if op == 'asl':
            c = a >> 7
            a = (a << 1) & 0xFF
        elif op == 'lsr':
            c = a & 1
            a = a >> 1
        elif op == 'rol':
            a, c = ((a << 1) | c) & 0xFF, a >> 7
        elif op == 'ror':
            a, c = (a >> 1) | (c << 7), a & 1
        elif op == 'asr':
            c = a & 1
            a = (a >> 1) | (a & 0x80)
        out.append([a, c, int(a == 0), a >> 7])
    return out
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]), ('rotate left with carry in', [65, 1, ['rol', 'rol']], [[131, 0, 0, 1], [6, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [4, 1, ['ror', 'ror']], [[130, 0, 0, 1], [65, 0, 0, 0]]), ('arithmetic right shift keeps sign', [197, 0, ['asr', 'asr', 'asr']], [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [5, 0, ['lsr', 'lsr']], [[2, 1, 0, 0], [1, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [86, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0]]), ('rotate left with carry in', [66, 1, ['rol', 'rol']], [[133, 0, 0, 1], [10, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [6, 1, ['ror', 'ror']], [[131, 0, 0, 1], [65, 1, 0, 0]]), ('arithmetic right shift keeps sign', [198, 0, ['asr', 'asr', 'asr']], [[227, 0, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [9, 0, ['lsr', 'lsr']], [[4, 1, 0, 0], [2, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [87, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[175, 0, 0, 1], [87, 1, 0, 0], [171, 1, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0]]), ('rotate left with carry in', [67, 1, ['rol', 'rol']], [[135, 0, 0, 1], [14, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [8, 1, ['ror', 'ror']], [[132, 0, 0, 1], [66, 0, 0, 0]]), ('arithmetic right shift keeps sign', [199, 0, ['asr', 'asr', 'asr']], [[227, 1, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [13, 0, ['lsr', 'lsr']], [[6, 1, 0, 0], [3, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [88, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[177, 0, 0, 1], [88, 1, 0, 0], [172, 0, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1]]), ('rotate left with carry in', [68, 1, ['rol', 'rol']], [[137, 0, 0, 1], [18, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [10, 1, ['ror', 'ror']], [[133, 0, 0, 1], [66, 1, 0, 0]]), ('arithmetic right shift keeps sign', [200, 0, ['asr', 'asr', 'asr']], [[228, 0, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [17, 0, ['lsr', 'lsr']], [[8, 1, 0, 0], [4, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [89, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[179, 0, 0, 1], [89, 1, 0, 0], [172, 1, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1], [64, 1, 0, 0]]), ('rotate left with carry in', [69, 1, ['rol', 'rol']], [[139, 0, 0, 1], [22, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [12, 1, ['ror', 'ror']], [[134, 0, 0, 1], [67, 0, 0, 0]]), ('arithmetic right shift keeps sign', [201, 0, ['asr', 'asr', 'asr']], [[228, 1, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [21, 0, ['lsr', 'lsr']], [[10, 1, 0, 0], [5, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [90, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[181, 0, 0, 1], [90, 1, 0, 0], [173, 0, 0, 1], [214, 1, 0, 1], [172, 1, 0, 1]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
rotate left through carry[[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]][[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]Passed
rotate left with carry in[[131, 0, 0, 1], [6, 1, 0, 0]][[131, 0, 0, 1], [6, 1, 0, 0]]Passed
rotate right through carry[[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]][[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]Passed
rotate right carry into bit seven[[130, 0, 0, 1], [65, 0, 0, 0]][[130, 0, 0, 1], [65, 0, 0, 0]]Passed
arithmetic right shift keeps sign[[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]][[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]Passed
logical right shift carry[[2, 1, 0, 0], [1, 0, 0, 0]][[2, 1, 0, 0], [1, 0, 0, 0]]Passed
shift left carry out[[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]][[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]Passed
mixed sequence[[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]][[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]]Passed

SHA-256 / de8760719a9feb4472a520069eb43b45e11f0d828e5e7b90f90a7deae26e520b

Verification & scope

A deterministic bounded teaching model of one emulator rule; the instruction semantics are a stipulated contract inspired by common ISAs and are not a claim of cycle-exact or architectural conformance. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.

Observations recorded using Python 3.12.14 at 2026-09-29T14:51:20.658061+00:00.

Case digest / 508d9c199357c4a529fe18fe12b2b3a26551364108708d0febfbd440b64b408b