FAILURE MAP
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FA-89731 / Instruction set emulation / Open access

Writable CSR range treated as read-only · case 01

Writes to CSRs whose top bits are 10 trap as illegal.

Verified by executionVariant 1 · 11 checks per implementationDownload source bundle ↓JSON ↗

ROOT CAUSE

Any CSR with bit 11 set is considered read-only.

VERIFIED REPAIR

Only top bits 11 (both set) mean read-only.

Unsuccessful approach: Testing bit 10 alone marks the 01 range read-only instead.

Case contract

Input [priv, csr, op, rs1, value, csrs] with priv 0 (U), 1 (S) or 3 (M) and csrs mapping decimal-string CSR numbers to values. Unknown CSR -> 'illegal'. Bits 9:8 of the CSR number give the lowest privilege allowed; bits 11:10 equal to 3 mark it read-only. csrrw/csrrwi always write; csrrs/csrrc/csrrsi/csrrci write only when the rs1 field (register index, or the 5-bit immediate for i-forms) is nonzero. Writing a read-only CSR -> 'illegal'. Operand: the register value, or the rs1 field itself for i-forms. New value: rw -> operand, rs -> old | operand, rc -> old & ~operand. Return ['ok', old, new (old if no write)].

Why this case matters

Privileged-architecture emulation must reject illegal CSR accesses exactly, since operating systems probe CSRs and rely on traps.

1 / The failure

Exit 1
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    priv, csr, op, rs1, val, csrs = args
    if str(csr) not in csrs:
        return 'illegal'
    ro = (csr >> 10) & 3 >= 2
    need = (csr >> 8) & 3
    if priv < need:
        return 'illegal'
    imm = op.endswith('i')
    v = rs1 if imm else val
    writes = op in ('csrrw', 'csrrwi') or rs1 != 0
    if ro and writes:
        return 'illegal'
    old = csrs[str(csr)]
    base = op[:5]
    if base == 'csrrw': new = v
    elif base == 'csrrs': new = old | v
    else: new = old & ~v & 0xFFFFFFFF
    return ['ok', old, new if writes else old]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('machine writes machine csr', [3, 768, 'csrrw', 5, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 9]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 124, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 100, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 4, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 4]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 292, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 10, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 10]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 125, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 101, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 5, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 5]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 293, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 11, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 11]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 126, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 102, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 6]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 294, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 12, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 12]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 127, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 103, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 7, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 7]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 295, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 13, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 13]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 128, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 104, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 8, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 8]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 296, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
machine writes machine csr['ok', 6144, 9]['ok', 6144, 9]Passed
user reads read-only counter['ok', 2457, 2457]['ok', 2457, 2457]Passed
user set-bits with nonzero rs1 on read-onlyillegalillegalPassed
supervisor touches machine csrillegalillegalPassed
immediate write to read-only hart idillegalillegalPassed
clear bits in user csr['ok', 5, 1]['ok', 5, 1]Passed
set bits immediate form['ok', 5, 7]['ok', 5, 7]Passed
custom machine read-write csr['ok', 7, 4]['ok', 7, 4]Passed
machine counter is writableillegal['ok', 50, 4]Failed
user reads supervisor csrillegalillegalPassed
missing csrillegalillegalPassed

SHA-256 / 3deeae9685ee1f5e62e63663c96849e44e8cd7f30f65dbe1b952e803e309339d

2 / The unsuccessful fix

Exit 1
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    priv, csr, op, rs1, val, csrs = args
    if str(csr) not in csrs:
        return 'illegal'
    ro = (csr >> 10) & 1 == 1
    need = (csr >> 8) & 3
    if priv < need:
        return 'illegal'
    imm = op.endswith('i')
    v = rs1 if imm else val
    writes = op in ('csrrw', 'csrrwi') or rs1 != 0
    if ro and writes:
        return 'illegal'
    old = csrs[str(csr)]
    base = op[:5]
    if base == 'csrrw': new = v
    elif base == 'csrrs': new = old | v
    else: new = old & ~v & 0xFFFFFFFF
    return ['ok', old, new if writes else old]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('machine writes machine csr', [3, 768, 'csrrw', 5, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 9]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 124, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 100, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 4, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 4]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 292, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 10, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 10]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 125, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 101, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 5, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 5]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 293, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 11, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 11]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 126, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 102, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 6]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 294, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 12, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 12]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 127, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 103, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 7, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 7]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 295, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 13, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 13]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 128, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 104, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 8, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 8]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 296, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
machine writes machine csr['ok', 6144, 9]['ok', 6144, 9]Passed
user reads read-only counter['ok', 2457, 2457]['ok', 2457, 2457]Passed
user set-bits with nonzero rs1 on read-onlyillegalillegalPassed
supervisor touches machine csrillegalillegalPassed
immediate write to read-only hart idillegalillegalPassed
clear bits in user csr['ok', 5, 1]['ok', 5, 1]Passed
set bits immediate form['ok', 5, 7]['ok', 5, 7]Passed
custom machine read-write csrillegal['ok', 7, 4]Failed
machine counter is writable['ok', 50, 4]['ok', 50, 4]Passed
user reads supervisor csrillegalillegalPassed
missing csrillegalillegalPassed

SHA-256 / df8d8b4b4cd1c64305cf6cdc6e688dde76b24ab14231a2e716860ebb463d181e

3 / The verified repair

Exit 0
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    priv, csr, op, rs1, val, csrs = args
    if str(csr) not in csrs:
        return 'illegal'
    ro = (csr >> 10) & 3 == 3
    need = (csr >> 8) & 3
    if priv < need:
        return 'illegal'
    imm = op.endswith('i')
    v = rs1 if imm else val
    writes = op in ('csrrw', 'csrrwi') or rs1 != 0
    if ro and writes:
        return 'illegal'
    old = csrs[str(csr)]
    base = op[:5]
    if base == 'csrrw': new = v
    elif base == 'csrrs': new = old | v
    else: new = old & ~v & 0xFFFFFFFF
    return ['ok', old, new if writes else old]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('machine writes machine csr', [3, 768, 'csrrw', 5, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 9]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 124, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 100, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 4, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 4]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 292, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 10, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 10]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 125, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 101, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 5, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 5]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 293, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 11, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 11]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 126, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 102, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 6]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 294, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 12, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 12]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 127, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 103, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 7, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 7]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 295, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 13, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 13]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 128, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 104, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 8, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 8]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 296, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
machine writes machine csr['ok', 6144, 9]['ok', 6144, 9]Passed
user reads read-only counter['ok', 2457, 2457]['ok', 2457, 2457]Passed
user set-bits with nonzero rs1 on read-onlyillegalillegalPassed
supervisor touches machine csrillegalillegalPassed
immediate write to read-only hart idillegalillegalPassed
clear bits in user csr['ok', 5, 1]['ok', 5, 1]Passed
set bits immediate form['ok', 5, 7]['ok', 5, 7]Passed
custom machine read-write csr['ok', 7, 4]['ok', 7, 4]Passed
machine counter is writable['ok', 50, 4]['ok', 50, 4]Passed
user reads supervisor csrillegalillegalPassed
missing csrillegalillegalPassed

SHA-256 / 2571a01f6b2f110db846c098e60a1678b738deceec272c1f8f4e9b6b028df191

Verification & scope

A deterministic bounded teaching model of one emulator rule; the instruction semantics are a stipulated contract inspired by common ISAs and are not a claim of cycle-exact or architectural conformance. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.

Observations recorded using Python 3.12.14 at 2026-09-29T14:51:20.050393+00:00.

Case digest / ccce674776265b19b9a42c0f08bbd0fb2487188ac2d4d8ccdc09c9c9abb6e3b6