FA-89725 / Instruction set emulation / Member archive

Writes to r0 are kept · case 05

After addi r0, r0 is nonzero and later reads of r0 are wrong.

Member previewVariant 5 · 3 implementations · 6 checks per implementation

Case contract

Input [prog, limit]: word-indexed instructions at byte addresses 4*i: addi rt rs imm, beq/bne/beql rs rt off16, j index, nop, halt; 8 registers with r0 hardwired to 0. Branch target = branch address + 4 + (sign-extended off16 << 2). The instruction after a branch or jump (its delay slot) always executes before control transfers, except that a not-taken beql skips (annuls) its slot. j target = ((pc+4) & 0xF0000000) | (index << 2). Addresses outside the program behave as halt. Return [executed pcs, registers].

Why this case matters

Emulating MIPS-style pipelines requires executing the architectural delay slot and computing targets from the slot address.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
zero register and jump	`[[0, 4, 8, 12, 16, 20, 24], [12, 7, 0, 0, 13, 14, 15, 0]]`	`[[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]`	Failed

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This record includes three runnable implementations, regression fixtures, execution results, and source hashes.

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