Understand the failure.
Verify the repair.
Small, reproducible software failures. The broken implementation, the fix that didn’t work, and the one that passed—preserved together.
Explore the cases ↓How results are verified ↗WHAT THE ARCHIVE CONTAINS
100840 executable cases. 20168 are open.
Every case records the implementation that fails, the fix that did not work, and the repair that passed its checks—with recorded outputs and source hashes. This release adds 100840 cases across 20168 failure mechanisms and 254 domains.
The open tier gives you the failure and the unsuccessful fix for one case in every mechanism. The remaining 80672 cases, 5 variants per mechanism, are member-only: the verified repair, its recorded checks, and the full fixture suite are held in the member archive. Read the methodology ↗
A RECORD OF WHAT WENT WRONG
Browse the archive / 100840
Sign extension tests bit 7 for every size · case 01
Halfword and word loads sign-extend based on their low byte.
Sign extension tests bit 7 for every size · case 02
Halfword and word loads sign-extend based on their low byte.
Sign extension tests bit 7 for every size · case 03
Halfword and word loads sign-extend based on their low byte.
Sign extension tests bit 7 for every size · case 04
Halfword and word loads sign-extend based on their low byte.
Sign extension tests bit 7 for every size · case 05
Halfword and word loads sign-extend based on their low byte.
All accesses require word alignment · case 01
Byte and halfword accesses at legal unaligned addresses trap.
All accesses require word alignment · case 02
Byte and halfword accesses at legal unaligned addresses trap.
All accesses require word alignment · case 03
Byte and halfword accesses at legal unaligned addresses trap.
All accesses require word alignment · case 04
Byte and halfword accesses at legal unaligned addresses trap.
All accesses require word alignment · case 05
Byte and halfword accesses at legal unaligned addresses trap.
Every stored byte receives the low byte · case 01
sw and sh replicate the least significant byte across the whole access.
Every stored byte receives the low byte · case 02
sw and sh replicate the least significant byte across the whole access.
Every stored byte receives the low byte · case 03
sw and sh replicate the least significant byte across the whole access.
Every stored byte receives the low byte · case 04
sw and sh replicate the least significant byte across the whole access.
Every stored byte receives the low byte · case 05
sw and sh replicate the least significant byte across the whole access.
Unsigned higher ignores the zero flag · case 01
hi is true after comparing equal values.
Unsigned higher ignores the zero flag · case 02
hi is true after comparing equal values.
Unsigned higher ignores the zero flag · case 03
hi is true after comparing equal values.
Unsigned higher ignores the zero flag · case 04
hi is true after comparing equal values.
Unsigned higher ignores the zero flag · case 05
hi is true after comparing equal values.
Lower-or-same requires both borrow and equality · case 01
ls is false for strictly lower operands.
Lower-or-same requires both borrow and equality · case 02
ls is false for strictly lower operands.
Lower-or-same requires both borrow and equality · case 03
ls is false for strictly lower operands.
Lower-or-same requires both borrow and equality · case 04
ls is false for strictly lower operands.
Lower-or-same requires both borrow and equality · case 05
ls is false for strictly lower operands.
Signed comparison ignores overflow · case 01
ge gives the wrong answer when the subtraction overflowed.
Signed comparison ignores overflow · case 02
ge gives the wrong answer when the subtraction overflowed.
Signed comparison ignores overflow · case 03
ge gives the wrong answer when the subtraction overflowed.
Signed comparison ignores overflow · case 04
ge gives the wrong answer when the subtraction overflowed.
Signed comparison ignores overflow · case 05
ge gives the wrong answer when the subtraction overflowed.
Signed greater-than true on equality · case 01
gt is true after comparing equal values.
Signed greater-than true on equality · case 02
gt is true after comparing equal values.
Signed greater-than true on equality · case 03
gt is true after comparing equal values.
Signed greater-than true on equality · case 04
gt is true after comparing equal values.
Signed greater-than true on equality · case 05
gt is true after comparing equal values.
Signed less-or-equal needs both zero and sign mismatch · case 01
le is false for strictly smaller signed values.
Signed less-or-equal needs both zero and sign mismatch · case 02
le is false for strictly smaller signed values.
Signed less-or-equal needs both zero and sign mismatch · case 03
le is false for strictly smaller signed values.
Signed less-or-equal needs both zero and sign mismatch · case 04
le is false for strictly smaller signed values.
Signed less-or-equal needs both zero and sign mismatch · case 05
le is false for strictly smaller signed values.
Writes to the zero register stick · case 01
After writing x0, later instructions reading x0 see a nonzero value.
Writes to the zero register stick · case 02
After writing x0, later instructions reading x0 see a nonzero value.
Writes to the zero register stick · case 03
After writing x0, later instructions reading x0 see a nonzero value.
Writes to the zero register stick · case 04
After writing x0, later instructions reading x0 see a nonzero value.
Writes to the zero register stick · case 05
After writing x0, later instructions reading x0 see a nonzero value.
Register values exceed 32 bits · case 01
Additions that overflow keep a 33rd bit and negative results stay negative.
Register values exceed 32 bits · case 02
Additions that overflow keep a 33rd bit and negative results stay negative.
Register values exceed 32 bits · case 03
Additions that overflow keep a 33rd bit and negative results stay negative.
Register values exceed 32 bits · case 04
Additions that overflow keep a 33rd bit and negative results stay negative.
Register values exceed 32 bits · case 05
Additions that overflow keep a 33rd bit and negative results stay negative.
slt compares register values as unsigned · case 01
slt reports -1 as greater than 1.
slt compares register values as unsigned · case 02
slt reports -1 as greater than 1.
slt compares register values as unsigned · case 03
slt reports -1 as greater than 1.
slt compares register values as unsigned · case 04
slt reports -1 as greater than 1.
slt compares register values as unsigned · case 05
slt reports -1 as greater than 1.
sltiu compares against a negative immediate · case 01
sltiu rd, rs, -1 is always false instead of true for every value except all ones.
sltiu compares against a negative immediate · case 02
sltiu rd, rs, -1 is always false instead of true for every value except all ones.
sltiu compares against a negative immediate · case 03
sltiu rd, rs, -1 is always false instead of true for every value except all ones.
sltiu compares against a negative immediate · case 04
sltiu rd, rs, -1 is always false instead of true for every value except all ones.
sltiu compares against a negative immediate · case 05
sltiu rd, rs, -1 is always false instead of true for every value except all ones.
srai shifts in zeros · case 01
Arithmetic right shift of a negative value produces a large positive value.
srai shifts in zeros · case 02
Arithmetic right shift of a negative value produces a large positive value.
srai shifts in zeros · case 03
Arithmetic right shift of a negative value produces a large positive value.
srai shifts in zeros · case 04
Arithmetic right shift of a negative value produces a large positive value.
srai shifts in zeros · case 05
Arithmetic right shift of a negative value produces a large positive value.
slli shift amount not masked to five bits · case 01
Shifting left by 32 or more clears the register instead of using the low five bits.
slli shift amount not masked to five bits · case 02
Shifting left by 32 or more clears the register instead of using the low five bits.
slli shift amount not masked to five bits · case 03
Shifting left by 32 or more clears the register instead of using the low five bits.
slli shift amount not masked to five bits · case 04
Shifting left by 32 or more clears the register instead of using the low five bits.
slli shift amount not masked to five bits · case 05
Shifting left by 32 or more clears the register instead of using the low five bits.
NMI treated as level triggered · case 01
Holding the NMI line high re-enters the NMI handler on every step.
NMI treated as level triggered · case 02
Holding the NMI line high re-enters the NMI handler on every step.
NMI treated as level triggered · case 03
Holding the NMI line high re-enters the NMI handler on every step.
NMI treated as level triggered · case 04
Holding the NMI line high re-enters the NMI handler on every step.
NMI treated as level triggered · case 05
Holding the NMI line high re-enters the NMI handler on every step.
IRQ ignores the interrupt disable flag · case 01
An IRQ is taken while I is set.
IRQ ignores the interrupt disable flag · case 02
An IRQ is taken while I is set.
IRQ ignores the interrupt disable flag · case 03
An IRQ is taken while I is set.
IRQ ignores the interrupt disable flag · case 04
An IRQ is taken while I is set.
IRQ ignores the interrupt disable flag · case 05
An IRQ is taken while I is set.
IRQ entry leaves interrupts enabled · case 01
A level IRQ that is still asserted re-enters its handler immediately.
IRQ entry leaves interrupts enabled · case 02
A level IRQ that is still asserted re-enters its handler immediately.
IRQ entry leaves interrupts enabled · case 03
A level IRQ that is still asserted re-enters its handler immediately.
IRQ entry leaves interrupts enabled · case 04
A level IRQ that is still asserted re-enters its handler immediately.
IRQ entry leaves interrupts enabled · case 05
A level IRQ that is still asserted re-enters its handler immediately.
Return from interrupt pops pc before flags · case 01
rti restores the saved flag into pc and the saved pc into I.
Return from interrupt pops pc before flags · case 02
rti restores the saved flag into pc and the saved pc into I.
Return from interrupt pops pc before flags · case 03
rti restores the saved flag into pc and the saved pc into I.
Return from interrupt pops pc before flags · case 04
rti restores the saved flag into pc and the saved pc into I.
Return from interrupt pops pc before flags · case 05
rti restores the saved flag into pc and the saved pc into I.
NMI edge detector not updated when the NMI is taken · case 01
A held NMI line is seen as a new edge on the step after entry.
NMI edge detector not updated when the NMI is taken · case 02
A held NMI line is seen as a new edge on the step after entry.
NMI edge detector not updated when the NMI is taken · case 03
A held NMI line is seen as a new edge on the step after entry.
NMI edge detector not updated when the NMI is taken · case 04
A held NMI line is seen as a new edge on the step after entry.
NMI edge detector not updated when the NMI is taken · case 05
A held NMI line is seen as a new edge on the step after entry.
SIB base 5 displacement omitted · case 01
A SIB-addressed instruction with no base register is decoded four bytes short.
SIB base 5 displacement omitted · case 02
A SIB-addressed instruction with no base register is decoded four bytes short.
SIB base 5 displacement omitted · case 03
A SIB-addressed instruction with no base register is decoded four bytes short.
SIB base 5 displacement omitted · case 04
A SIB-addressed instruction with no base register is decoded four bytes short.
SIB base 5 displacement omitted · case 05
A SIB-addressed instruction with no base register is decoded four bytes short.
INSPECTABLE BY DESIGN
Every result has a runnable source.
Runnable implementations with recorded outputs, source hashes, and explicit contracts. Related variants share a failure mechanism and belong together in evaluation splits.
Read the methodology ↗