FAILURE MAP
← Case archive

FA-89581 / Instruction set emulation / Open access

IRQ entry leaves interrupts enabled · case 01

A level IRQ that is still asserted re-enters its handler immediately.

Verified by executionVariant 1 · 7 checks per implementationDownload source bundle ↓JSON ↗

ROOT CAUSE

The IRQ entry sequence does not set I.

THE FAILURE

The IRQ entry sequence does not set I.

Unsuccessful approach: Copying the saved I value back keeps interrupts enabled in the handler.

Case contract

Input [pc, i, steps] with steps [irq, nmi, instr]. Each step: an NMI 0->1 edge (the line starts low) is taken first; otherwise a high IRQ line is taken when the I flag is 0; otherwise the instruction runs (nop/cli/sei advance pc by 1, rti pops I then pc if the stack is non-empty). Taking an interrupt pushes pc then I, sets I=1 and jumps to 0x9000 (NMI) or 0x8000 (IRQ). The NMI edge detector samples the line every step. Return [event, pc, I] per step.

Why this case matters

Interrupt controllers in CPU emulators must separate edge- and level-triggered sources, masking and nesting to reproduce handler timing.

1 / The failure

Exit 1
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    pc, i, steps = args
    stack = []
    nprev = 0
    log = []
    for irq, nmi, ins in steps:
        if nprev == 0 and nmi == 1:
            stack += [pc, i]
            i = 1
            pc = 0x9000
            ev = 'nmi'
        elif irq == 1 and i == 0:
            stack += [pc, i]
            pc = 0x8000
            ev = 'irq'
        elif ins == 'rti' and stack:
            i = stack.pop()
            pc = stack.pop()
            ev = 'rti'
        else:
            if ins == 'cli': i = 0
            elif ins == 'sei': i = 1
            pc += 1
            ev = ins
        nprev = nmi
        log.append([ev, pc, i])
    return log
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [769, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 769, 0], ['rti', 770, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])], [('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0], ['nop', 260, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [770, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 770, 0], ['rti', 771, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0], ['nop', 1282, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['nop', 36867, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])], [('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0], ['nop', 260, 0], ['nop', 261, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [771, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 771, 0], ['rti', 772, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0], ['nop', 1282, 0], ['nop', 1283, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['nop', 36867, 1], ['nop', 36868, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])], [('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0], ['nop', 260, 0], ['nop', 261, 0], ['nop', 262, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [772, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 772, 0], ['rti', 773, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0], ['nop', 1282, 0], ['nop', 1283, 0], ['nop', 1284, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['nop', 36867, 1], ['nop', 36868, 1], ['nop', 36869, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])], [('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0], ['nop', 260, 0], ['nop', 261, 0], ['nop', 262, 0], ['nop', 263, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [773, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 773, 0], ['rti', 774, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0], ['nop', 1282, 0], ['nop', 1283, 0], ['nop', 1284, 0], ['nop', 1285, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['nop', 36867, 1], ['nop', 36868, 1], ['nop', 36869, 1], ['nop', 36870, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
masked irq waits for cli[['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 0], ['rti', 258, 0], ['nop', 259, 0]][['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0]]Failed
nmi is edge triggered[['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]][['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]Passed
nmi wins over irq[['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 769, 0], ['rti', 770, 0]][['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 769, 0], ['rti', 770, 0]]Passed
irq handler masks nested irq[['irq', 32768, 0], ['irq', 32768, 0], ['irq', 32768, 0], ['rti', 32768, 0], ['nop', 32769, 0]][['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]Failed
nmi nested inside irq[['irq', 32768, 0], ['nop', 32769, 0], ['nmi', 36864, 1], ['rti', 32769, 0], ['rti', 1280, 0], ['nop', 1281, 0]][['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0]]Failed
nmi held across entry[['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['rti', 1536, 1]][['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['rti', 1536, 1]]Passed
sei then irq[['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 0]][['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]]Failed

SHA-256 / 432e6d4500215c361504195306e3f2eae6152156730530c27821f2869ec78d21

2 / The unsuccessful fix

Exit 1
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    pc, i, steps = args
    stack = []
    nprev = 0
    log = []
    for irq, nmi, ins in steps:
        if nprev == 0 and nmi == 1:
            stack += [pc, i]
            i = 1
            pc = 0x9000
            ev = 'nmi'
        elif irq == 1 and i == 0:
            stack += [pc, i]
            i = stack[-1]
            pc = 0x8000
            ev = 'irq'
        elif ins == 'rti' and stack:
            i = stack.pop()
            pc = stack.pop()
            ev = 'rti'
        else:
            if ins == 'cli': i = 0
            elif ins == 'sei': i = 1
            pc += 1
            ev = ins
        nprev = nmi
        log.append([ev, pc, i])
    return log
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [769, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 769, 0], ['rti', 770, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])], [('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0], ['nop', 260, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [770, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 770, 0], ['rti', 771, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0], ['nop', 1282, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['nop', 36867, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])], [('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0], ['nop', 260, 0], ['nop', 261, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [771, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 771, 0], ['rti', 772, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0], ['nop', 1282, 0], ['nop', 1283, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['nop', 36867, 1], ['nop', 36868, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])], [('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0], ['nop', 260, 0], ['nop', 261, 0], ['nop', 262, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [772, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 772, 0], ['rti', 773, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0], ['nop', 1282, 0], ['nop', 1283, 0], ['nop', 1284, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['nop', 36867, 1], ['nop', 36868, 1], ['nop', 36869, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])], [('masked irq waits for cli', [256, 1, [[1, 0, 'nop'], [1, 0, 'cli'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0], ['nop', 260, 0], ['nop', 261, 0], ['nop', 262, 0], ['nop', 263, 0]]), ('nmi is edge triggered', [512, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'nop'], [0, 1, 'nop']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]), ('nmi wins over irq', [773, 0, [[1, 1, 'nop'], [1, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 773, 0], ['rti', 774, 0]]), ('irq handler masks nested irq', [1024, 0, [[1, 0, 'nop'], [1, 0, 'nop'], [1, 0, 'nop'], [0, 0, 'rti'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]), ('nmi nested inside irq', [1280, 0, [[1, 0, 'nop'], [0, 0, 'nop'], [0, 1, 'nop'], [0, 1, 'rti'], [0, 0, 'rti'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop'], [0, 0, 'nop']]], [['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0], ['nop', 1282, 0], ['nop', 1283, 0], ['nop', 1284, 0], ['nop', 1285, 0]]), ('nmi held across entry', [1536, 1, [[0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 1, 'nop'], [0, 0, 'rti']]], [['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['nop', 36867, 1], ['nop', 36868, 1], ['nop', 36869, 1], ['nop', 36870, 1], ['rti', 1536, 1]]), ('sei then irq', [1792, 0, [[0, 0, 'sei'], [1, 0, 'nop'], [0, 0, 'cli'], [1, 0, 'nop']]], [['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
masked irq waits for cli[['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 0], ['rti', 258, 0], ['nop', 259, 0]][['nop', 257, 1], ['cli', 258, 0], ['irq', 32768, 1], ['rti', 258, 0], ['nop', 259, 0]]Failed
nmi is edge triggered[['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]][['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 512, 1], ['nop', 513, 1], ['nmi', 36864, 1]]Passed
nmi wins over irq[['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 769, 0], ['rti', 770, 0]][['nmi', 36864, 1], ['nop', 36865, 1], ['rti', 769, 0], ['rti', 770, 0]]Passed
irq handler masks nested irq[['irq', 32768, 0], ['irq', 32768, 0], ['irq', 32768, 0], ['rti', 32768, 0], ['nop', 32769, 0]][['irq', 32768, 1], ['nop', 32769, 1], ['nop', 32770, 1], ['rti', 1024, 0], ['nop', 1025, 0]]Failed
nmi nested inside irq[['irq', 32768, 0], ['nop', 32769, 0], ['nmi', 36864, 1], ['rti', 32769, 0], ['rti', 1280, 0], ['nop', 1281, 0]][['irq', 32768, 1], ['nop', 32769, 1], ['nmi', 36864, 1], ['rti', 32769, 1], ['rti', 1280, 0], ['nop', 1281, 0]]Failed
nmi held across entry[['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['rti', 1536, 1]][['nmi', 36864, 1], ['nop', 36865, 1], ['nop', 36866, 1], ['rti', 1536, 1]]Passed
sei then irq[['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 0]][['sei', 1793, 1], ['nop', 1794, 1], ['cli', 1795, 0], ['irq', 32768, 1]]Failed

SHA-256 / 809dbd052ada8775954e026014913af770d5deec25acf3cf0ea1702284b4b778

HELD IN THE MEMBER ARCHIVE

The verified repair and its recorded checks are member-only.

This mechanism has 7 recorded checks per implementation. The open-access tier publishes the failure and the unsuccessful fix; the repaired source that passes every check, and the observations that prove it, are available to members.

Every case sharing this mechanism uses the same contract and the same repair, so this one record is held back for all of them.

Member access is invitation-based. Sign in with your invited account to inspect the repair.

Sign in to the archive ↗

Verification & scope

A deterministic bounded teaching model of one emulator rule; the instruction semantics are a stipulated contract inspired by common ISAs and are not a claim of cycle-exact or architectural conformance. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.

Observations recorded using Python 3.12.14 at 2026-09-29T14:51:18.783925+00:00.

Case digest / 9dc5856d366f293a986e790957d43f990160235e8d264f8a0d3af84edd252fa0