FA-89552 / Instruction set emulation / Member archive

slt compares register values as unsigned · case 02

slt reports -1 as greater than 1.

Member previewVariant 2 · 3 implementations · 8 checks per implementation

Case contract

Input [prog]: [op, rd, a, b] with ops addi (x[a]+b), add, sub, lui (b<<12), slt (signed), sltu (unsigned), sltiu (x[a] < b sign-extended then taken unsigned), srai, srli, slli (shift amount b & 31). Registers x0..x31 start at 0 and hold unsigned 32-bit values; x0 always reads 0 and writes to it are discarded. Return sorted [index, value] of nonzero registers.

Why this case matters

Every RISC emulator implements a register file with a zero register and 32-bit wrapping arithmetic on a host with unbounded integers.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
signed and unsigned compare	`[[1, 4294967295], [2, 3], [5, 1]]`	`[[1, 4294967295], [2, 3], [3, 1]]`	Failed

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This record includes three runnable implementations, regression fixtures, execution results, and source hashes.

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