FA-98547 / KV cache position mapping / Member archive
Ring writes wrap at capacity · case 02
A cache write past the final slot escapes the circular buffer.
Case contract
Map each inclusive logical position to (position, (slot_origin + position - logical_origin) modulo capacity). Capacity is positive.
Why this case matters
A small in-memory model makes the cache address contract explicit for a serving component.
One recorded failure
Sample boundary fixtureThis sample comes from the broken implementation of a controlled reproducer.
| Boundary fixture | Actual | Expected | Outcome |
|---|---|---|---|
| wrap once | [[10, 2], [11, 3], [12, 4]] | [[10, 2], [11, 3], [12, 0]] | Failed |
MEMBER ARCHIVE
The complete case is available to members.
This record includes three runnable implementations, regression fixtures, execution results, and source hashes.
Member access is invitation-based. Sign in with your invited account to inspect the sources.
Sign in to the archive ↗