FA-92335 / PLC ladder logic scan cycles / Member archive

Overflow trap clearing rung is evaluated before the math rung · case 05

An overflow in the same scan as the clearing rung still halts the processor.

Member previewVariant 5 · 3 implementations · 8 checks per implementation

Case contract

16-bit INT math rung followed by a later fault-clearing rung, one op per scan; ops is a list of [a, b, ADD|SUB|MUL, clear]. A result outside -32768..32767 sets the overflow bit V for that instruction and the overflow trap; the stored result is saturated to 32767/-32768 when clamp is set or wrapped as 16-bit two's complement otherwise. V is recomputed per instruction. The later rung clears the trap when clear is true; a trap still set at end of scan halts the processor. Return [result, V, trap] per scan, then "halted" and stop if faulted.

Why this case matters

Ladder programs are executed as repeated scans; each defect here changes what a rung, timer, counter or data-table instruction reports on a particular scan, which is how commissioning and field faults are actually observed.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
regression: scenario 4	`[[-8224, true, true], "halted"]`	`[[-8224, true, false], [25763, true, false], [-199, false, false], [-28081, true, true], "halted"]`	Failed

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