FA-92264 / PLC ladder logic scan cycles / Member archive
Free-running clock timer captures its start tick while disabled · case 04
After an idle period the timer finishes immediately because time before the enable is counted.
Case contract
Delay timer built on a 16-bit free-running clock register (ticks wrap from 65535 to 0). samples is a list of [enable, clock] read each scan. The first enabled scan captures the start tick; elapsed is (clock - start) modulo 65536. Done latches once elapsed >= preset and stays set while enabled even if the elapsed value later wraps. A disabled scan clears start and done. Return [done, elapsed capped at preset once done] per scan, [False, 0] when disabled.
Why this case matters
Ladder programs are executed as repeated scans; each defect here changes what a rung, timer, counter or data-table instruction reports on a particular scan, which is how commissioning and field faults are actually observed.
One recorded failure
Sample boundary fixtureThis sample comes from the broken implementation of a controlled reproducer.
| Boundary fixture | Actual | Expected | Outcome |
|---|---|---|---|
| regression: scenario 3 | [[false, 0], [false, 3390], [false, 0], [false, 108], [false, 0], [false, 0], [false, 8011], [false, 20339], [false, 20436], [false, 38703], [false, 2411], [false, 2430], [false, 2479]] | [[false, 0], [false, 0], [false, 0], [false, 0], [false, 0], [false, 0], [false, 8011], [false, 20339], [false, 20436], [false, 38703], [false, 2411], [false, 2430], [false, 2479]] | Failed |
MEMBER ARCHIVE
The complete case is available to members.
This record includes three runnable implementations, regression fixtures, execution results, and source hashes.
Member access is invitation-based. Sign in with your invited account to inspect the sources.
Sign in to the archive ↗