FA-92262 / PLC ladder logic scan cycles / Member archive

Free-running clock timer captures its start tick while disabled · case 02

After an idle period the timer finishes immediately because time before the enable is counted.

Member previewVariant 2 · 3 implementations · 8 checks per implementation

Case contract

Delay timer built on a 16-bit free-running clock register (ticks wrap from 65535 to 0). samples is a list of [enable, clock] read each scan. The first enabled scan captures the start tick; elapsed is (clock - start) modulo 65536. Done latches once elapsed >= preset and stays set while enabled even if the elapsed value later wraps. A disabled scan clears start and done. Return [done, elapsed capped at preset once done] per scan, [False, 0] when disabled.

Why this case matters

Ladder programs are executed as repeated scans; each defect here changes what a rung, timer, counter or data-table instruction reports on a particular scan, which is how commissioning and field faults are actually observed.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
regression: scenario 1	`[[false, 0], [false, 0], [false, 153], [false, 315], [false, 0], [true, 1000], [true, 1000], [true, 1000]]`	`[[false, 0], [false, 0], [false, 0], [false, 162], [false, 0], [false, 0], [false, 153], [true, 1000]]`	Failed

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