FAILURE MAP
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FA-89801 / Instruction set emulation / Open access

Arithmetic right shift loses the sign bit · case 01

asr of a negative value turns it positive.

Verified by executionVariant 1 · 8 checks per implementationDownload source bundle ↓JSON ↗

ROOT CAUSE

The shift does not replicate bit 7.

THE FAILURE

The shift does not replicate bit 7.

Unsuccessful approach: Copying bit 6 replicates the wrong bit.

Case contract

Input [a, c, ops] with ops asl, lsr, rol, ror, asr on an 8-bit value and a carry bit. asl: C = bit 7, shift left. lsr: C = bit 0, shift right with 0. rol: shift left, bit 0 = old C, new C = old bit 7. ror: shift right, bit 7 = old C, new C = old bit 0. asr: C = bit 0, shift right keeping bit 7. Report [A, C, Z, N] after each op.

Why this case matters

Rotate-through-carry instructions implement multi-byte shifts in 8-bit code; emulating them with circular rotates or sequenced updates breaks arithmetic libraries.

1 / The failure

Exit 1
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    a, c, ops = args
    out = []
    for op in ops:
        if op == 'asl':
            c = a >> 7
            a = (a << 1) & 0xFF
        elif op == 'lsr':
            c = a & 1
            a = a >> 1
        elif op == 'rol':
            a, c = ((a << 1) | c) & 0xFF, a >> 7
        elif op == 'ror':
            a, c = (a >> 1) | (c << 7), a & 1
        elif op == 'asr':
            c = a & 1
            a = a >> 1
        out.append([a, c, int(a == 0), a >> 7])
    return out
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]), ('rotate left with carry in', [65, 1, ['rol', 'rol']], [[131, 0, 0, 1], [6, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [4, 1, ['ror', 'ror']], [[130, 0, 0, 1], [65, 0, 0, 0]]), ('arithmetic right shift keeps sign', [197, 0, ['asr', 'asr', 'asr']], [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [5, 0, ['lsr', 'lsr']], [[2, 1, 0, 0], [1, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [86, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0]]), ('rotate left with carry in', [66, 1, ['rol', 'rol']], [[133, 0, 0, 1], [10, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [6, 1, ['ror', 'ror']], [[131, 0, 0, 1], [65, 1, 0, 0]]), ('arithmetic right shift keeps sign', [198, 0, ['asr', 'asr', 'asr']], [[227, 0, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [9, 0, ['lsr', 'lsr']], [[4, 1, 0, 0], [2, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [87, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[175, 0, 0, 1], [87, 1, 0, 0], [171, 1, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0]]), ('rotate left with carry in', [67, 1, ['rol', 'rol']], [[135, 0, 0, 1], [14, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [8, 1, ['ror', 'ror']], [[132, 0, 0, 1], [66, 0, 0, 0]]), ('arithmetic right shift keeps sign', [199, 0, ['asr', 'asr', 'asr']], [[227, 1, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [13, 0, ['lsr', 'lsr']], [[6, 1, 0, 0], [3, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [88, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[177, 0, 0, 1], [88, 1, 0, 0], [172, 0, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1]]), ('rotate left with carry in', [68, 1, ['rol', 'rol']], [[137, 0, 0, 1], [18, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [10, 1, ['ror', 'ror']], [[133, 0, 0, 1], [66, 1, 0, 0]]), ('arithmetic right shift keeps sign', [200, 0, ['asr', 'asr', 'asr']], [[228, 0, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [17, 0, ['lsr', 'lsr']], [[8, 1, 0, 0], [4, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [89, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[179, 0, 0, 1], [89, 1, 0, 0], [172, 1, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1], [64, 1, 0, 0]]), ('rotate left with carry in', [69, 1, ['rol', 'rol']], [[139, 0, 0, 1], [22, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [12, 1, ['ror', 'ror']], [[134, 0, 0, 1], [67, 0, 0, 0]]), ('arithmetic right shift keeps sign', [201, 0, ['asr', 'asr', 'asr']], [[228, 1, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [21, 0, ['lsr', 'lsr']], [[10, 1, 0, 0], [5, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [90, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[181, 0, 0, 1], [90, 1, 0, 0], [173, 0, 0, 1], [214, 1, 0, 1], [172, 1, 0, 1]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
rotate left through carry[[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]][[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]Passed
rotate left with carry in[[131, 0, 0, 1], [6, 1, 0, 0]][[131, 0, 0, 1], [6, 1, 0, 0]]Passed
rotate right through carry[[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]][[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]Passed
rotate right carry into bit seven[[130, 0, 0, 1], [65, 0, 0, 0]][[130, 0, 0, 1], [65, 0, 0, 0]]Passed
arithmetic right shift keeps sign[[98, 1, 0, 0], [49, 0, 0, 0], [24, 1, 0, 0]][[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]Failed
logical right shift carry[[2, 1, 0, 0], [1, 0, 0, 0]][[2, 1, 0, 0], [1, 0, 0, 0]]Passed
shift left carry out[[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]][[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]Passed
mixed sequence[[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [85, 1, 0, 0], [170, 0, 0, 1]][[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]]Failed

SHA-256 / fa811a0cfd31a199d6ddff1441065965ed9559e9b947687bb3a7ed8986b800dc

2 / The unsuccessful fix

Exit 1
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    a, c, ops = args
    out = []
    for op in ops:
        if op == 'asl':
            c = a >> 7
            a = (a << 1) & 0xFF
        elif op == 'lsr':
            c = a & 1
            a = a >> 1
        elif op == 'rol':
            a, c = ((a << 1) | c) & 0xFF, a >> 7
        elif op == 'ror':
            a, c = (a >> 1) | (c << 7), a & 1
        elif op == 'asr':
            c = a & 1
            a = (a >> 1) | (a & 0x40)
        out.append([a, c, int(a == 0), a >> 7])
    return out
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]), ('rotate left with carry in', [65, 1, ['rol', 'rol']], [[131, 0, 0, 1], [6, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [4, 1, ['ror', 'ror']], [[130, 0, 0, 1], [65, 0, 0, 0]]), ('arithmetic right shift keeps sign', [197, 0, ['asr', 'asr', 'asr']], [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [5, 0, ['lsr', 'lsr']], [[2, 1, 0, 0], [1, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [86, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0]]), ('rotate left with carry in', [66, 1, ['rol', 'rol']], [[133, 0, 0, 1], [10, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [6, 1, ['ror', 'ror']], [[131, 0, 0, 1], [65, 1, 0, 0]]), ('arithmetic right shift keeps sign', [198, 0, ['asr', 'asr', 'asr']], [[227, 0, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [9, 0, ['lsr', 'lsr']], [[4, 1, 0, 0], [2, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [87, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[175, 0, 0, 1], [87, 1, 0, 0], [171, 1, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0]]), ('rotate left with carry in', [67, 1, ['rol', 'rol']], [[135, 0, 0, 1], [14, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [8, 1, ['ror', 'ror']], [[132, 0, 0, 1], [66, 0, 0, 0]]), ('arithmetic right shift keeps sign', [199, 0, ['asr', 'asr', 'asr']], [[227, 1, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [13, 0, ['lsr', 'lsr']], [[6, 1, 0, 0], [3, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [88, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[177, 0, 0, 1], [88, 1, 0, 0], [172, 0, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1]]), ('rotate left with carry in', [68, 1, ['rol', 'rol']], [[137, 0, 0, 1], [18, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [10, 1, ['ror', 'ror']], [[133, 0, 0, 1], [66, 1, 0, 0]]), ('arithmetic right shift keeps sign', [200, 0, ['asr', 'asr', 'asr']], [[228, 0, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [17, 0, ['lsr', 'lsr']], [[8, 1, 0, 0], [4, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [89, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[179, 0, 0, 1], [89, 1, 0, 0], [172, 1, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1], [64, 1, 0, 0]]), ('rotate left with carry in', [69, 1, ['rol', 'rol']], [[139, 0, 0, 1], [22, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [12, 1, ['ror', 'ror']], [[134, 0, 0, 1], [67, 0, 0, 0]]), ('arithmetic right shift keeps sign', [201, 0, ['asr', 'asr', 'asr']], [[228, 1, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [21, 0, ['lsr', 'lsr']], [[10, 1, 0, 0], [5, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [90, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[181, 0, 0, 1], [90, 1, 0, 0], [173, 0, 0, 1], [214, 1, 0, 1], [172, 1, 0, 1]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)
Boundary fixtureActualExpectedOutcome
rotate left through carry[[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]][[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]Passed
rotate left with carry in[[131, 0, 0, 1], [6, 1, 0, 0]][[131, 0, 0, 1], [6, 1, 0, 0]]Passed
rotate right through carry[[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]][[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]Passed
rotate right carry into bit seven[[130, 0, 0, 1], [65, 0, 0, 0]][[130, 0, 0, 1], [65, 0, 0, 0]]Passed
arithmetic right shift keeps sign[[98, 1, 0, 0], [113, 0, 0, 0], [120, 1, 0, 0]][[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]Failed
logical right shift carry[[2, 1, 0, 0], [1, 0, 0, 0]][[2, 1, 0, 0], [1, 0, 0, 0]]Passed
shift left carry out[[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]][[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]Passed
mixed sequence[[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [85, 1, 0, 0], [170, 0, 0, 1]][[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]]Failed

SHA-256 / 94dd8b3e1f29b7ac33d9cf58cfcd71e13c2e3981c52bde56756f8f3ae754c61f

HELD IN THE MEMBER ARCHIVE

The verified repair and its recorded checks are member-only.

This mechanism has 8 recorded checks per implementation. The open-access tier publishes the failure and the unsuccessful fix; the repaired source that passes every check, and the observations that prove it, are available to members.

Every case sharing this mechanism uses the same contract and the same repair, so this one record is held back for all of them.

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Verification & scope

A deterministic bounded teaching model of one emulator rule; the instruction semantics are a stipulated contract inspired by common ISAs and are not a claim of cycle-exact or architectural conformance. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.

Observations recorded using Python 3.12.14 at 2026-09-29T14:51:20.708146+00:00.

Case digest / ced54e5d683f0afcfd4a2fc00d72c5580fc709146f0d39dc1118f0c718ed5575