FA-68124 / Traffic signal timing plans / Member archive

Dual-ring barrier sequencing: lead-lag is keyed on the second phase of the pair · case 04

Dual-ring barrier sequencing returns a wrong result when lead-lag is keyed on the second phase of the pair.

Member previewVariant 4 · 3 implementations · 8 checks per implementation

Case contract

Input {ring1: [[1,d],[2,d],[3,d],[4,d]], ring2: [[5,d],[6,d],[7,d],[8,d]] with durations including clearance, calls, lag}. Phases 1-2/5-6 are left of the barrier and 3-4/7-8 right of it. On each side both rings start together at the barrier; if the first phase of a ring's pair is in lag the pair is swapped. Phases without calls are skipped and take no time. Both rings cross a barrier together when the slower ring finishes. Return {starts: sorted [phase, start], cycle}.

Why this case matters

Signal timing arithmetic is exact and integer or rational; a wrong rule silently produces unsafe or inefficient timing plans.

One recorded failure

Sample boundary fixture

This sample comes from the broken implementation of a controlled reproducer.

Boundary fixture	Actual	Expected	Outcome
timing oracle 0	`{"cycle": 107, "starts": [[2, 0], [3, 67], [4, 32], [8, 32]]}`	`{"cycle": 107, "starts": [[2, 0], [3, 32], [4, 72], [8, 32]]}`	Failed

MEMBER ARCHIVE

The complete case is available to members.

This record includes three runnable implementations, regression fixtures, execution results, and source hashes.

Member access is invitation-based. Sign in with your invited account to inspect the sources.