FA-49970 / PCM sample encoding / Member archive
Pcm i2s delayed capture: one clock delay · case 05
Serial PCM captures the clock-delay bit as sample MSB.
Case contract
Capture a stipulated I2S-like slot with one delay clock, MSB-first signed PCM payload and explicit trailing slot bits; reject incomplete slots.
Why this case matters
Offline PCM interchange uses these exact bounded packet and sample representation decisions.
One recorded failure
Sample boundary fixtureThis sample comes from the broken implementation of a controlled reproducer.
| Boundary fixture | Actual | Expected | Outcome |
|---|---|---|---|
| oracle 1 | [[5, [0]], [-5, [0]]] | [[-6, [0]], [7, [0]]] | Failed |
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This record includes three runnable implementations, regression fixtures, execution results, and source hashes.
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