broken_source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    prog, limit = args
    r = [0] * 8
    pc = 0
    trace = []
    pending = None
    steps = 0
    while steps < limit:
        steps += 1
        ins = prog[pc // 4] if 0 <= pc // 4 < len(prog) else ['halt']
        trace.append(pc)
        op = ins[0]
        nxt = pc + 4
        if op == 'halt':
            break
        if op == 'addi':
            if ins[1]:
                r[ins[1]] = r[ins[2]] + ins[3]
        elif op in ('beq', 'bne', 'beql'):
            taken = (r[ins[1]] == r[ins[2]]) == (op != 'bne')
            off = ins[3] - 0x10000 if ins[3] & 0x8000 else ins[3]
            tgt = pc + 4 + (off << 2)
            if op == 'beql' and not taken:
                nxt = pc + 8
            else:
                nxt = tgt if taken else pc + 4
        elif op == 'j':
            pending = ((pc + 4) & 0xF0000000) | (ins[1] << 2)
        if pending is not None and op not in ('beq', 'bne', 'beql', 'j'):
            nxt = pending
            pending = None
        pc = nxt
    return [trace, r]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 2], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 4, 2, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 3], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 3, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 1], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 2, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 3], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 6, 3, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 4], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 4, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 2], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 3, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 4], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 8, 4, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 5], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 5, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 3], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 4, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 5], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 10, 5, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 6], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 6, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 4], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 5, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 6], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 12, 6, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 7], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 5], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 6, 0]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    prog, limit = args
    r = [0] * 8
    pc = 0
    trace = []
    pending = None
    steps = 0
    while steps < limit:
        steps += 1
        ins = prog[pc // 4] if 0 <= pc // 4 < len(prog) else ['halt']
        trace.append(pc)
        op = ins[0]
        nxt = pc + 4
        if op == 'halt':
            break
        if op == 'addi':
            if ins[1]:
                r[ins[1]] = r[ins[2]] + ins[3]
        elif op in ('beq', 'bne', 'beql'):
            taken = (r[ins[1]] == r[ins[2]]) == (op != 'bne')
            off = ins[3] - 0x10000 if ins[3] & 0x8000 else ins[3]
            tgt = pc + 4 + (off << 2)
            if op == 'beql' and not taken:
                nxt = pc + 8
            else:
                nxt, pending = (tgt, None) if taken else (pc + 4, pc + 8)
        elif op == 'j':
            pending = ((pc + 4) & 0xF0000000) | (ins[1] << 2)
        if pending is not None and op not in ('beq', 'bne', 'beql', 'j'):
            nxt = pending
            pending = None
        pc = nxt
    return [trace, r]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 2], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 4, 2, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 3], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 3, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 1], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 2, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 3], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 6, 3, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 4], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 4, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 2], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 3, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 4], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 8, 4, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 5], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 5, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 3], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 4, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 5], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 10, 5, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 6], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 6, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 4], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 5, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 6], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 12, 6, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 7], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 5], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 6, 0]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

prompt:
The instruction after a taken branch never executes.

Input [prog, limit]: word-indexed instructions at byte addresses 4*i: addi rt rs imm, beq/bne/beql rs rt off16, j index, nop, halt; 8 registers with r0 hardwired to 0. Branch target = branch address + 4 + (sign-extended off16 << 2). The instruction after a branch or jump (its delay slot) always executes before control transfers, except that a not-taken beql skips (annuls) its slot. j target = ((pc+4) & 0xF0000000) | (index << 2). Addresses outside the program behave as halt. Return [executed pcs, registers].

split: open-access


broken_source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    prog, limit = args
    r = [0] * 8
    pc = 0
    trace = []
    pending = None
    steps = 0
    while steps < limit:
        steps += 1
        ins = prog[pc // 4] if 0 <= pc // 4 < len(prog) else ['halt']
        trace.append(pc)
        op = ins[0]
        nxt = pc + 4
        if op == 'halt':
            break
        if op == 'addi':
            if ins[1]:
                r[ins[1]] = r[ins[2]] + ins[3]
        elif op in ('beq', 'bne', 'beql'):
            taken = (r[ins[1]] == r[ins[2]]) == (op != 'bne')
            off = ins[3] - 0x10000 if ins[3] & 0x8000 else ins[3]
            tgt = pc + 4 + (off << 2)
            if False and not taken:
                nxt = pc + 8
            else:
                pending = tgt if taken else pc + 8
        elif op == 'j':
            pending = ((pc + 4) & 0xF0000000) | (ins[1] << 2)
        if pending is not None and op not in ('beq', 'bne', 'beql', 'j'):
            nxt = pending
            pending = None
        pc = nxt
    return [trace, r]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 2], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 4, 2, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 3], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 3, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 1], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 2, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 3], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 6, 3, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 4], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 4, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 2], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 3, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 4], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 8, 4, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 5], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 5, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 3], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 4, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 5], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 10, 5, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 6], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 6, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 4], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 5, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 6], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 12, 6, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 7], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 5], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 6, 0]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

meaning: Fixture-count band, not measured model difficulty

deps: stdlib

source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    prog, limit = args
    r = [0] * 8
    pc = 0
    trace = []
    pending = None
    steps = 0
    while steps < limit:
        steps += 1
        ins = prog[pc // 4] if 0 <= pc // 4 < len(prog) else ['halt']
        trace.append(pc)
        op = ins[0]
        nxt = pc + 4
        if op == 'halt':
            break
        if op == 'addi':
            if ins[1]:
                r[ins[1]] = r[ins[2]] + ins[3]
        elif op in ('beq', 'bne', 'beql'):
            taken = (r[ins[1]] == r[ins[2]]) == (op != 'bne')
            off = ins[3] - 0x10000 if ins[3] & 0x8000 else ins[3]
            tgt = pc + 4 + (off << 2)
            if op == 'beql' and taken:
                nxt = pc + 8
            else:
                pending = tgt if taken else pc + 8
        elif op == 'j':
            pending = ((pc + 4) & 0xF0000000) | (ins[1] << 2)
        if pending is not None and op not in ('beq', 'bne', 'beql', 'j'):
            nxt = pending
            pending = None
        pc = nxt
    return [trace, r]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 2], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 4, 2, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 3], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 3, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 1], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 2, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 3], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 6, 3, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 4], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 4, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 2], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 3, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 4], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 8, 4, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 5], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 5, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 3], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 4, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 5], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 10, 5, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 6], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 6, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 4], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 5, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 6], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 12, 6, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 7], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 5], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 6, 0]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

prompt:
The delay slot of a not-taken branch-likely instruction still executes.

Input [prog, limit]: word-indexed instructions at byte addresses 4*i: addi rt rs imm, beq/bne/beql rs rt off16, j index, nop, halt; 8 registers with r0 hardwired to 0. Branch target = branch address + 4 + (sign-extended off16 << 2). The instruction after a branch or jump (its delay slot) always executes before control transfers, except that a not-taken beql skips (annuls) its slot. j target = ((pc+4) & 0xF0000000) | (index << 2). Addresses outside the program behave as halt. Return [executed pcs, registers].

split: open-access


broken_source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    prog, limit = args
    r = [0] * 8
    pc = 0
    trace = []
    pending = None
    steps = 0
    while steps < limit:
        steps += 1
        ins = prog[pc // 4] if 0 <= pc // 4 < len(prog) else ['halt']
        trace.append(pc)
        op = ins[0]
        nxt = pc + 4
        if op == 'halt':
            break
        if op == 'addi':
            if ins[1]:
                r[ins[1]] = r[ins[2]] + ins[3]
        elif op in ('beq', 'bne', 'beql'):
            taken = (r[ins[1]] == r[ins[2]]) == (op != 'bne')
            off = ins[3]
            tgt = pc + 4 + (off << 2)
            if op == 'beql' and not taken:
                nxt = pc + 8
            else:
                pending = tgt if taken else pc + 8
        elif op == 'j':
            pending = ((pc + 4) & 0xF0000000) | (ins[1] << 2)
        if pending is not None and op not in ('beq', 'bne', 'beql', 'j'):
            nxt = pending
            pending = None
        pc = nxt
    return [trace, r]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 2], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 4, 2, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 3], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 3, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 1], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 2, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 3], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 6, 3, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 4], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 4, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 2], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 3, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 4], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 8, 4, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 5], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 5, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 3], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 4, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 5], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 10, 5, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 6], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 6, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 4], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 5, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 6], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 12, 6, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 7], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 5], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 6, 0]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    prog, limit = args
    r = [0] * 8
    pc = 0
    trace = []
    pending = None
    steps = 0
    while steps < limit:
        steps += 1
        ins = prog[pc // 4] if 0 <= pc // 4 < len(prog) else ['halt']
        trace.append(pc)
        op = ins[0]
        nxt = pc + 4
        if op == 'halt':
            break
        if op == 'addi':
            if ins[1]:
                r[ins[1]] = r[ins[2]] + ins[3]
        elif op in ('beq', 'bne', 'beql'):
            taken = (r[ins[1]] == r[ins[2]]) == (op != 'bne')
            off = ins[3] - 0x8000 if ins[3] & 0x8000 else ins[3]
            tgt = pc + 4 + (off << 2)
            if op == 'beql' and not taken:
                nxt = pc + 8
            else:
                pending = tgt if taken else pc + 8
        elif op == 'j':
            pending = ((pc + 4) & 0xF0000000) | (ins[1] << 2)
        if pending is not None and op not in ('beq', 'bne', 'beql', 'j'):
            nxt = pending
            pending = None
        pc = nxt
    return [trace, r]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 2], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 4, 2, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 3], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 3, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 1], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 2, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 3], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 6, 3, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 4], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 4, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 2], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 3, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 4], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 8, 4, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 5], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 5, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 3], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 4, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 5], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 10, 5, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 6], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 6, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 4], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 5, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 6], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 12, 6, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 7], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 5], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 6, 0]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

prompt:
A backward loop branch jumps far forward out of the program.

Input [prog, limit]: word-indexed instructions at byte addresses 4*i: addi rt rs imm, beq/bne/beql rs rt off16, j index, nop, halt; 8 registers with r0 hardwired to 0. Branch target = branch address + 4 + (sign-extended off16 << 2). The instruction after a branch or jump (its delay slot) always executes before control transfers, except that a not-taken beql skips (annuls) its slot. j target = ((pc+4) & 0xF0000000) | (index << 2). Addresses outside the program behave as halt. Return [executed pcs, registers].

split: open-access


broken_source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    prog, limit = args
    r = [0] * 8
    pc = 0
    trace = []
    pending = None
    steps = 0
    while steps < limit:
        steps += 1
        ins = prog[pc // 4] if 0 <= pc // 4 < len(prog) else ['halt']
        trace.append(pc)
        op = ins[0]
        nxt = pc + 4
        if op == 'halt':
            break
        if op == 'addi':
            if True:
                r[ins[1]] = r[ins[2]] + ins[3]
        elif op in ('beq', 'bne', 'beql'):
            taken = (r[ins[1]] == r[ins[2]]) == (op != 'bne')
            off = ins[3] - 0x10000 if ins[3] & 0x8000 else ins[3]
            tgt = pc + 4 + (off << 2)
            if op == 'beql' and not taken:
                nxt = pc + 8
            else:
                pending = tgt if taken else pc + 8
        elif op == 'j':
            pending = ((pc + 4) & 0xF0000000) | (ins[1] << 2)
        if pending is not None and op not in ('beq', 'bne', 'beql', 'j'):
            nxt = pending
            pending = None
        pc = nxt
    return [trace, r]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 2], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 4, 2, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 3], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 3, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 1], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 2, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 3], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 6, 3, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 4], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 4, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 2], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 3, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 4], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 8, 4, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 5], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 5, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 3], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 4, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 5], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 10, 5, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 6], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 6, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 4], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 5, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 6], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 12, 6, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 7], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 5], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 6, 0]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    prog, limit = args
    r = [0] * 8
    pc = 0
    trace = []
    pending = None
    steps = 0
    while steps < limit:
        steps += 1
        ins = prog[pc // 4] if 0 <= pc // 4 < len(prog) else ['halt']
        trace.append(pc)
        op = ins[0]
        nxt = pc + 4
        if op == 'halt':
            break
        if op == 'addi':
            if ins[1] or ins[3] == 5:
                r[ins[1]] = r[ins[2]] + ins[3]
        elif op in ('beq', 'bne', 'beql'):
            taken = (r[ins[1]] == r[ins[2]]) == (op != 'bne')
            off = ins[3] - 0x10000 if ins[3] & 0x8000 else ins[3]
            tgt = pc + 4 + (off << 2)
            if op == 'beql' and not taken:
                nxt = pc + 8
            else:
                pending = tgt if taken else pc + 8
        elif op == 'j':
            pending = ((pc + 4) & 0xF0000000) | (ins[1] << 2)
        if pending is not None and op not in ('beq', 'bne', 'beql', 'j'):
            nxt = pending
            pending = None
        pc = nxt
    return [trace, r]
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 2], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 4, 2, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 3], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 3, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 1], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 2, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 3], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 6, 3, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 4], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 4, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 2], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 3, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 4], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 8, 4, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 5], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 5, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 3], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 4, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 5], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 10, 5, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 6], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 6, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 4], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 5, 0]])], [('forward taken beq', [[['addi', 1, 0, 3], ['beq', 0, 0, 2], ['addi', 2, 2, 1], ['addi', 3, 0, 9], ['halt']], 40], [[0, 4, 8, 16], [0, 3, 1, 0, 0, 0, 0, 0]]), ('backward counted loop', [[['addi', 1, 0, 6], ['addi', 2, 2, 2], ['addi', 1, 1, -1], ['bne', 1, 0, 65533], ['addi', 3, 3, 1], ['halt']], 60], [[0, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 4, 8, 12, 16, 20], [0, 0, 12, 6, 0, 0, 0, 0]]), ('branch likely not taken annuls slot', [[['addi', 1, 0, 1], ['beql', 1, 0, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['halt']], 40], [[0, 4, 12, 16], [0, 1, 0, 4, 0, 0, 0, 0]]), ('branch likely taken runs slot', [[['addi', 1, 0, 1], ['beql', 1, 1, 2], ['addi', 2, 0, 7], ['addi', 3, 0, 4], ['addi', 4, 0, 5], ['halt']], 40], [[0, 4, 8, 16, 20], [0, 1, 7, 0, 5, 0, 0, 0]]), ('zero register and jump', [[['addi', 1, 0, 7], ['addi', 0, 1, 5], ['addi', 4, 0, 1], ['j', 5], ['addi', 5, 4, 1], ['addi', 6, 0, 3], ['halt']], 40], [[0, 4, 8, 12, 16, 20, 24], [0, 7, 0, 0, 1, 2, 3, 0]]), ('bne with nop slot', [[['addi', 1, 0, 1], ['bne', 1, 0, 3], ['nop'], ['addi', 7, 0, 1], ['halt'], ['addi', 6, 1, 5], ['halt']], 40], [[0, 4, 8, 20, 24], [0, 1, 0, 0, 0, 0, 6, 0]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

prompt:
After addi r0, r0 is nonzero and later reads of r0 are wrong.

Input [prog, limit]: word-indexed instructions at byte addresses 4*i: addi rt rs imm, beq/bne/beql rs rt off16, j index, nop, halt; 8 registers with r0 hardwired to 0. Branch target = branch address + 4 + (sign-extended off16 << 2). The instruction after a branch or jump (its delay slot) always executes before control transfers, except that a not-taken beql skips (annuls) its slot. j target = ((pc+4) & 0xF0000000) | (index << 2). Addresses outside the program behave as halt. Return [executed pcs, registers].

split: open-access


prompt:
Supervisor code can access machine CSRs.

Input [priv, csr, op, rs1, value, csrs] with priv 0 (U), 1 (S) or 3 (M) and csrs mapping decimal-string CSR numbers to values. Unknown CSR -> 'illegal'. Bits 9:8 of the CSR number give the lowest privilege allowed; bits 11:10 equal to 3 mark it read-only. csrrw/csrrwi always write; csrrs/csrrc/csrrsi/csrrci write only when the rs1 field (register index, or the 5-bit immediate for i-forms) is nonzero. Writing a read-only CSR -> 'illegal'. Operand: the register value, or the rs1 field itself for i-forms. New value: rw -> operand, rs -> old | operand, rc -> old & ~operand. Return ['ok', old, new (old if no write)].

split: open-access


prompt:
Writes to CSRs whose top bits are 10 trap as illegal.

Input [priv, csr, op, rs1, value, csrs] with priv 0 (U), 1 (S) or 3 (M) and csrs mapping decimal-string CSR numbers to values. Unknown CSR -> 'illegal'. Bits 9:8 of the CSR number give the lowest privilege allowed; bits 11:10 equal to 3 mark it read-only. csrrw/csrrwi always write; csrrs/csrrc/csrrsi/csrrci write only when the rs1 field (register index, or the 5-bit immediate for i-forms) is nonzero. Writing a read-only CSR -> 'illegal'. Operand: the register value, or the rs1 field itself for i-forms. New value: rw -> operand, rs -> old | operand, rc -> old & ~operand. Return ['ok', old, new (old if no write)].

split: open-access


prompt:
csrrs with rs1=x0 on a read-only counter traps, and a set with a zero-valued nonzero register does not.

Input [priv, csr, op, rs1, value, csrs] with priv 0 (U), 1 (S) or 3 (M) and csrs mapping decimal-string CSR numbers to values. Unknown CSR -> 'illegal'. Bits 9:8 of the CSR number give the lowest privilege allowed; bits 11:10 equal to 3 mark it read-only. csrrw/csrrwi always write; csrrs/csrrc/csrrsi/csrrci write only when the rs1 field (register index, or the 5-bit immediate for i-forms) is nonzero. Writing a read-only CSR -> 'illegal'. Operand: the register value, or the rs1 field itself for i-forms. New value: rw -> operand, rs -> old | operand, rc -> old & ~operand. Return ['ok', old, new (old if no write)].

split: open-access


prompt:
An immediate write of 0 to a read-only CSR does not trap.

Input [priv, csr, op, rs1, value, csrs] with priv 0 (U), 1 (S) or 3 (M) and csrs mapping decimal-string CSR numbers to values. Unknown CSR -> 'illegal'. Bits 9:8 of the CSR number give the lowest privilege allowed; bits 11:10 equal to 3 mark it read-only. csrrw/csrrwi always write; csrrs/csrrc/csrrsi/csrrci write only when the rs1 field (register index, or the 5-bit immediate for i-forms) is nonzero. Writing a read-only CSR -> 'illegal'. Operand: the register value, or the rs1 field itself for i-forms. New value: rw -> operand, rs -> old | operand, rc -> old & ~operand. Return ['ok', old, new (old if no write)].

split: open-access


prompt:
csrrc sets bits that were clear in the CSR.

Input [priv, csr, op, rs1, value, csrs] with priv 0 (U), 1 (S) or 3 (M) and csrs mapping decimal-string CSR numbers to values. Unknown CSR -> 'illegal'. Bits 9:8 of the CSR number give the lowest privilege allowed; bits 11:10 equal to 3 mark it read-only. csrrw/csrrwi always write; csrrs/csrrc/csrrsi/csrrci write only when the rs1 field (register index, or the 5-bit immediate for i-forms) is nonzero. Writing a read-only CSR -> 'illegal'. Operand: the register value, or the rs1 field itself for i-forms. New value: rw -> operand, rs -> old | operand, rc -> old & ~operand. Return ['ok', old, new (old if no write)].

split: open-access


prompt:
csrrsi sets the bits of an unrelated register value instead of the 5-bit immediate.

Input [priv, csr, op, rs1, value, csrs] with priv 0 (U), 1 (S) or 3 (M) and csrs mapping decimal-string CSR numbers to values. Unknown CSR -> 'illegal'. Bits 9:8 of the CSR number give the lowest privilege allowed; bits 11:10 equal to 3 mark it read-only. csrrw/csrrwi always write; csrrs/csrrc/csrrsi/csrrci write only when the rs1 field (register index, or the 5-bit immediate for i-forms) is nonzero. Writing a read-only CSR -> 'illegal'. Operand: the register value, or the rs1 field itself for i-forms. New value: rw -> operand, rs -> old | operand, rc -> old & ~operand. Return ['ok', old, new (old if no write)].

split: open-access


broken_source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    pc, priv, mie, mtvec, events = args
    mpie = mpp = mcause = mepc = 0
    log = []
    for ev in events:
        kind = ev[0]
        trap = None
        if kind == 'step':
            pc += 4
        elif kind == 'ecall':
            trap = 11
        elif kind == 'illegal':
            trap = 2
        elif kind == 'irq':
            if priv < 3 or mie:
                trap = (1 << 31) | ev[1]
        elif kind == 'mret':
            mie = mpie
            mpie = 1
            priv = mpp
            mpp = 0
            pc = mepc
        if trap is not None:
            mepc = pc
            mcause = trap
            mpie = mie
            mie = 0
            mpp = priv
            priv = 3
            base = mtvec & ~3
            pc = base + 4 * (trap & 0x7FFFFFFF) if (mtvec & 3) == 1 and trap >> 31 else base
        log.append([pc, priv, mie, mpie, mpp, mcause, mepc])
    return log
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('user ecall and return', [1028, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4354, [['ecall'], ['mret']]], [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1032, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1036, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1036], [4100, 3, 0, 1, 0, 8, 1036], [1036, 0, 1, 1, 0, 8, 1036]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4610, [['ecall'], ['mret']]], [[4608, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1036, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1040, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1040], [4100, 3, 0, 1, 0, 8, 1040], [1040, 0, 1, 1, 0, 8, 1040]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4866, [['ecall'], ['mret']]], [[4864, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1040, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1044, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1044], [4100, 3, 0, 1, 0, 8, 1044], [1044, 0, 1, 1, 0, 8, 1044]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5122, [['ecall'], ['mret']]], [[5120, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1044, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1048, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1048], [4100, 3, 0, 1, 0, 8, 1048], [1048, 0, 1, 1, 0, 8, 1048]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5378, [['ecall'], ['mret']]], [[5376, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096], [4116, 0, 1, 1, 0, 2, 4096]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

source:
"""Failure Map reference implementation. Python standard library only."""
import json

N = 1
observations = []
def solve(*args):
    pc, priv, mie, mtvec, events = args
    mpie = mpp = mcause = mepc = 0
    log = []
    for ev in events:
        kind = ev[0]
        trap = None
        if kind == 'step':
            pc += 4
        elif kind == 'ecall':
            trap = 8 + (priv > 0)
        elif kind == 'illegal':
            trap = 2
        elif kind == 'irq':
            if priv < 3 or mie:
                trap = (1 << 31) | ev[1]
        elif kind == 'mret':
            mie = mpie
            mpie = 1
            priv = mpp
            mpp = 0
            pc = mepc
        if trap is not None:
            mepc = pc
            mcause = trap
            mpie = mie
            mie = 0
            mpp = priv
            priv = 3
            base = mtvec & ~3
            pc = base + 4 * (trap & 0x7FFFFFFF) if (mtvec & 3) == 1 and trap >> 31 else base
        log.append([pc, priv, mie, mpie, mpp, mcause, mepc])
    return log
def check(label, actual, expected):
    observations.append({"check": label, "actual": actual, "expected": expected, "passed": actual == expected})
fixtures = [[('user ecall and return', [1028, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4354, [['ecall'], ['mret']]], [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1032, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1036, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1036], [4100, 3, 0, 1, 0, 8, 1036], [1036, 0, 1, 1, 0, 8, 1036]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4610, [['ecall'], ['mret']]], [[4608, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1036, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1040, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1040], [4100, 3, 0, 1, 0, 8, 1040], [1040, 0, 1, 1, 0, 8, 1040]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4866, [['ecall'], ['mret']]], [[4864, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1040, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1044, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1044], [4100, 3, 0, 1, 0, 8, 1044], [1044, 0, 1, 1, 0, 8, 1044]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5122, [['ecall'], ['mret']]], [[5120, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1044, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1048, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1048], [4100, 3, 0, 1, 0, 8, 1048], [1048, 0, 1, 1, 0, 8, 1048]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5378, [['ecall'], ['mret']]], [[5376, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096], [4116, 0, 1, 1, 0, 2, 4096]])]]
for label, args, expected in fixtures[N-1]:
    check(label, solve(*args), expected)
print(json.dumps({"observations": observations, "passed": all(x["passed"] for x in observations)}, ensure_ascii=False))
raise SystemExit(0 if all(x["passed"] for x in observations) else 1)

prompt:
User and supervisor system calls carry the machine-mode cause code.

Input [pc, priv, mie, mtvec, events]; MPIE, MPP, mcause, mepc start 0. step: pc += 4. ecall: exception cause 8 + priv (U 8, S 9, M 11). illegal: cause 2. irq k: interrupt cause 2^31 | k, taken only if priv < 3 or MIE. Trap: mepc = pc, mcause = cause, MPIE = MIE, MIE = 0, MPP = priv, priv = 3, pc = mtvec base (mtvec & ~3), plus 4*k for interrupts when mtvec mode (low 2 bits) is 1. mret: MIE = MPIE, MPIE = 1, priv = MPP, MPP = 0, pc = mepc. Return [pc, priv, MIE, MPIE, MPP, mcause, mepc] after each event.

split: open-access