{"abstract":"Remainders of negative dividends come out positive (-10 % 3 gives 2).","category":"Bytecode virtual machines","checks":8,"contract":"Each op is [name, a, b] over 32-bit two's complement ints: iadd/imul wrap; idiv truncates toward zero and MIN_VALUE / -1 wraps to MIN_VALUE; irem has the sign of the dividend; ishl/ishr/iushr use only the low five bits of the shift count, iushr shifts in zeros; ineg wraps. Division by zero yields \"ArithmeticException\", an unknown op \"VerifyError\".","evaluation_group":"w2-bytecode-virtual-machines-jvm-int32-arithmetic","failed_approach":"Using the sign of the divisor is exactly the host behaviour the opcode must avoid.","family":"w2-bytecode-virtual-machines-jvm-int32-arithmetic-irem-result-sign","id":"FA-89881","implementations":{"attempt":{"sha256":"7aa608499577380d4cfd7f0c2a41605ca2b62bc3f288ca094720318ca1992a26","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(ops):\n    def wrap(v):\n        v &= 0xFFFFFFFF\n        return v - 0x100000000 if v >= 0x80000000 else v\n    out = []\n    for op, a, b in ops:\n        if op == 'iadd':\n            out.append(wrap(a + b))\n        elif op == 'imul':\n            out.append(wrap(a * b))\n        elif op == 'idiv':\n            if b == 0:\n                out.append('ArithmeticException')\n            else:\n                q = abs(a) // abs(b)\n                out.append(wrap(q if (a < 0) == (b < 0) else -q))\n        elif op == 'irem':\n            if b == 0:\n                out.append('ArithmeticException')\n            else:\n                r = abs(a) % abs(b)\n                out.append(r if b >= 0 else -r)\n        elif op == 'ishl':\n            out.append(wrap(a << (b & 31)))\n        elif op == 'ishr':\n            out.append(a >> (b & 31))\n        elif op == 'iushr':\n            out.append(wrap((a & 0xFFFFFFFF) >> (b & 31)))\n        elif op == 'ineg':\n            out.append(wrap(-a))\n        else:\n            out.append('VerifyError')\n    return out\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\ncases = [[('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483646, 1], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -8, 2], ['idiv', 9, -2]],), [-4, -4]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483647, -1]],),\n   [-2147483648, 2147483647]),\n  ('irem takes the sign of the dividend', ([['irem', -10, 3], ['irem', 11, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 2, 32], ['ishl', 3, 34]],), [2, 12]),\n  ('iushr is a logical shift with masking', ([['iushr', -16, 28], ['iushr', -16, 37]],), [15, 134217727]),\n  ('division by zero', ([['idiv', 1, 0], ['irem', 1, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65537], ['ishr', -8, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [65536, -2, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483645, 2], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -9, 2], ['idiv', 11, -2]],), [-4, -5]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483646, -1]],),\n   [-2147483648, 2147483646]),\n  ('irem takes the sign of the dividend', ([['irem', -13, 3], ['irem', 14, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 3, 32], ['ishl', 3, 35]],), [3, 24]),\n  ('iushr is a logical shift with masking', ([['iushr', -32, 28], ['iushr', -16, 38]],), [15, 67108863]),\n  ('division by zero', ([['idiv', 2, 0], ['irem', 2, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65538], ['ishr', -16, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [131072, -4, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483644, 3], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -10, 2], ['idiv', 13, -2]],), [-5, -6]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483645, -1]],),\n   [-2147483648, 2147483645]),\n  ('irem takes the sign of the dividend', ([['irem', -16, 3], ['irem', 17, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 4, 32], ['ishl', 3, 36]],), [4, 48]),\n  ('iushr is a logical shift with masking', ([['iushr', -48, 28], ['iushr', -16, 39]],), [15, 33554431]),\n  ('division by zero', ([['idiv', 3, 0], ['irem', 3, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65539], ['ishr', -24, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [196608, -6, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483643, 4], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -11, 2], ['idiv', 15, -2]],), [-5, -7]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483644, -1]],),\n   [-2147483648, 2147483644]),\n  ('irem takes the sign of the dividend', ([['irem', -19, 3], ['irem', 20, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 5, 32], ['ishl', 3, 37]],), [5, 96]),\n  ('iushr is a logical shift with masking', ([['iushr', -64, 28], ['iushr', -16, 40]],), [15, 16777215]),\n  ('division by zero', ([['idiv', 4, 0], ['irem', 4, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65540], ['ishr', -32, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [262144, -8, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483642, 5], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -12, 2], ['idiv', 17, -2]],), [-6, -8]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483643, -1]],),\n   [-2147483648, 2147483643]),\n  ('irem takes the sign of the dividend', ([['irem', -22, 3], ['irem', 23, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 6, 32], ['ishl', 3, 38]],), [6, 192]),\n  ('iushr is a logical shift with masking', ([['iushr', -80, 28], ['iushr', -16, 41]],), [15, 8388607]),\n  ('division by zero', ([['idiv', 5, 0], ['irem', 5, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65541], ['ishr', -40, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [327680, -10, -2147483648, 'VerifyError'])]]\nfor label, args, expected in cases[N - 1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"broken":{"sha256":"99b590f69951a06bfa01dfcd0b497432c97606d21fc9fe10e63dbc544cb7650a","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(ops):\n    def wrap(v):\n        v &= 0xFFFFFFFF\n        return v - 0x100000000 if v >= 0x80000000 else v\n    out = []\n    for op, a, b in ops:\n        if op == 'iadd':\n            out.append(wrap(a + b))\n        elif op == 'imul':\n            out.append(wrap(a * b))\n        elif op == 'idiv':\n            if b == 0:\n                out.append('ArithmeticException')\n            else:\n                q = abs(a) // abs(b)\n                out.append(wrap(q if (a < 0) == (b < 0) else -q))\n        elif op == 'irem':\n            if b == 0:\n                out.append('ArithmeticException')\n            else:\n                r = abs(a) % abs(b)\n                out.append(a % b)\n        elif op == 'ishl':\n            out.append(wrap(a << (b & 31)))\n        elif op == 'ishr':\n            out.append(a >> (b & 31))\n        elif op == 'iushr':\n            out.append(wrap((a & 0xFFFFFFFF) >> (b & 31)))\n        elif op == 'ineg':\n            out.append(wrap(-a))\n        else:\n            out.append('VerifyError')\n    return out\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\ncases = [[('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483646, 1], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -8, 2], ['idiv', 9, -2]],), [-4, -4]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483647, -1]],),\n   [-2147483648, 2147483647]),\n  ('irem takes the sign of the dividend', ([['irem', -10, 3], ['irem', 11, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 2, 32], ['ishl', 3, 34]],), [2, 12]),\n  ('iushr is a logical shift with masking', ([['iushr', -16, 28], ['iushr', -16, 37]],), [15, 134217727]),\n  ('division by zero', ([['idiv', 1, 0], ['irem', 1, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65537], ['ishr', -8, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [65536, -2, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483645, 2], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -9, 2], ['idiv', 11, -2]],), [-4, -5]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483646, -1]],),\n   [-2147483648, 2147483646]),\n  ('irem takes the sign of the dividend', ([['irem', -13, 3], ['irem', 14, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 3, 32], ['ishl', 3, 35]],), [3, 24]),\n  ('iushr is a logical shift with masking', ([['iushr', -32, 28], ['iushr', -16, 38]],), [15, 67108863]),\n  ('division by zero', ([['idiv', 2, 0], ['irem', 2, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65538], ['ishr', -16, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [131072, -4, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483644, 3], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -10, 2], ['idiv', 13, -2]],), [-5, -6]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483645, -1]],),\n   [-2147483648, 2147483645]),\n  ('irem takes the sign of the dividend', ([['irem', -16, 3], ['irem', 17, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 4, 32], ['ishl', 3, 36]],), [4, 48]),\n  ('iushr is a logical shift with masking', ([['iushr', -48, 28], ['iushr', -16, 39]],), [15, 33554431]),\n  ('division by zero', ([['idiv', 3, 0], ['irem', 3, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65539], ['ishr', -24, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [196608, -6, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483643, 4], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -11, 2], ['idiv', 15, -2]],), [-5, -7]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483644, -1]],),\n   [-2147483648, 2147483644]),\n  ('irem takes the sign of the dividend', ([['irem', -19, 3], ['irem', 20, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 5, 32], ['ishl', 3, 37]],), [5, 96]),\n  ('iushr is a logical shift with masking', ([['iushr', -64, 28], ['iushr', -16, 40]],), [15, 16777215]),\n  ('division by zero', ([['idiv', 4, 0], ['irem', 4, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65540], ['ishr', -32, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [262144, -8, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483642, 5], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -12, 2], ['idiv', 17, -2]],), [-6, -8]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483643, -1]],),\n   [-2147483648, 2147483643]),\n  ('irem takes the sign of the dividend', ([['irem', -22, 3], ['irem', 23, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 6, 32], ['ishl', 3, 38]],), [6, 192]),\n  ('iushr is a logical shift with masking', ([['iushr', -80, 28], ['iushr', -16, 41]],), [15, 8388607]),\n  ('division by zero', ([['idiv', 5, 0], ['irem', 5, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65541], ['ishr', -40, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [327680, -10, -2147483648, 'VerifyError'])]]\nfor label, args, expected in cases[N - 1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"fixed":{"sha256":"d82463138cabe7da586d4868218a3ec371fb8a5d390b26b71191a945b77e3ddc","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(ops):\n    def wrap(v):\n        v &= 0xFFFFFFFF\n        return v - 0x100000000 if v >= 0x80000000 else v\n    out = []\n    for op, a, b in ops:\n        if op == 'iadd':\n            out.append(wrap(a + b))\n        elif op == 'imul':\n            out.append(wrap(a * b))\n        elif op == 'idiv':\n            if b == 0:\n                out.append('ArithmeticException')\n            else:\n                q = abs(a) // abs(b)\n                out.append(wrap(q if (a < 0) == (b < 0) else -q))\n        elif op == 'irem':\n            if b == 0:\n                out.append('ArithmeticException')\n            else:\n                r = abs(a) % abs(b)\n                out.append(r if a >= 0 else -r)\n        elif op == 'ishl':\n            out.append(wrap(a << (b & 31)))\n        elif op == 'ishr':\n            out.append(a >> (b & 31))\n        elif op == 'iushr':\n            out.append(wrap((a & 0xFFFFFFFF) >> (b & 31)))\n        elif op == 'ineg':\n            out.append(wrap(-a))\n        else:\n            out.append('VerifyError')\n    return out\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\ncases = [[('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483646, 1], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -8, 2], ['idiv', 9, -2]],), [-4, -4]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483647, -1]],),\n   [-2147483648, 2147483647]),\n  ('irem takes the sign of the dividend', ([['irem', -10, 3], ['irem', 11, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 2, 32], ['ishl', 3, 34]],), [2, 12]),\n  ('iushr is a logical shift with masking', ([['iushr', -16, 28], ['iushr', -16, 37]],), [15, 134217727]),\n  ('division by zero', ([['idiv', 1, 0], ['irem', 1, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65537], ['ishr', -8, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [65536, -2, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483645, 2], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -9, 2], ['idiv', 11, -2]],), [-4, -5]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483646, -1]],),\n   [-2147483648, 2147483646]),\n  ('irem takes the sign of the dividend', ([['irem', -13, 3], ['irem', 14, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 3, 32], ['ishl', 3, 35]],), [3, 24]),\n  ('iushr is a logical shift with masking', ([['iushr', -32, 28], ['iushr', -16, 38]],), [15, 67108863]),\n  ('division by zero', ([['idiv', 2, 0], ['irem', 2, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65538], ['ishr', -16, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [131072, -4, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483644, 3], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -10, 2], ['idiv', 13, -2]],), [-5, -6]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483645, -1]],),\n   [-2147483648, 2147483645]),\n  ('irem takes the sign of the dividend', ([['irem', -16, 3], ['irem', 17, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 4, 32], ['ishl', 3, 36]],), [4, 48]),\n  ('iushr is a logical shift with masking', ([['iushr', -48, 28], ['iushr', -16, 39]],), [15, 33554431]),\n  ('division by zero', ([['idiv', 3, 0], ['irem', 3, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65539], ['ishr', -24, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [196608, -6, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483643, 4], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -11, 2], ['idiv', 15, -2]],), [-5, -7]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483644, -1]],),\n   [-2147483648, 2147483644]),\n  ('irem takes the sign of the dividend', ([['irem', -19, 3], ['irem', 20, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 5, 32], ['ishl', 3, 37]],), [5, 96]),\n  ('iushr is a logical shift with masking', ([['iushr', -64, 28], ['iushr', -16, 40]],), [15, 16777215]),\n  ('division by zero', ([['idiv', 4, 0], ['irem', 4, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65540], ['ishr', -32, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [262144, -8, -2147483648, 'VerifyError'])],\n [('regression: iadd reaching MAX_VALUE',\n   ([['iadd', 2147483642, 5], ['iadd', 2147483647, 1]],),\n   [2147483647, -2147483648]),\n  ('idiv truncates toward zero', ([['idiv', -12, 2], ['idiv', 17, -2]],), [-6, -8]),\n  ('idiv MIN_VALUE by -1 overflows to MIN_VALUE',\n   ([['idiv', -2147483648, -1], ['idiv', -2147483643, -1]],),\n   [-2147483648, 2147483643]),\n  ('irem takes the sign of the dividend', ([['irem', -22, 3], ['irem', 23, -3]],), [-1, 2]),\n  ('ishl masks the shift count to five bits', ([['ishl', 6, 32], ['ishl', 3, 38]],), [6, 192]),\n  ('iushr is a logical shift with masking', ([['iushr', -80, 28], ['iushr', -16, 41]],), [15, 8388607]),\n  ('division by zero', ([['idiv', 5, 0], ['irem', 5, 0]],), ['ArithmeticException', 'ArithmeticException']),\n  ('controls: imul wrap, ishr, ineg MIN',\n   ([['imul', 65536, 65541], ['ishr', -40, 2], ['ineg', -2147483648, 0], ['bogus', 1, 1]],),\n   [327680, -10, -2147483648, 'VerifyError'])]]\nfor label, args, expected in cases[N - 1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"}},"limitations":"A deterministic, bounded teaching model of one bytecode virtual machine mechanism with a stipulated instruction encoding; it is not a production VM and claims no conformance to any real specification. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.","method":"Deterministic executable model with adversarial boundary fixtures.","provenance":{"created_by":"Failure Map","dependencies":"Python standard library","family":"w2-bytecode-virtual-machines-jvm-int32-arithmetic-irem-result-sign","generated_at":"2026-09-29T14:51:21.412228+00:00","license":"CC0-1.0","python":"3.12.14","seed":1,"split":"open-access"},"relevance":"Bytecode integer opcodes must reproduce fixed-width semantics that host-language integers do not.","repair":"Compute the magnitude remainder and give it the sign of the dividend.","root_cause":"The host modulo operator takes the sign of the divisor.","sha256":"f1ddc6da2f57a91c221fcb2998f4efeb5abeff1801c6973c33a3b06db824df84","title":"JVM int32 opcodes: irem follows the divisor sign · case 01","variant":1,"variant_policy":"Five numbered records share a model and may reuse boundary fixtures.","verification":{"attempt":{"elapsed_ms":41.645,"exit_code":1,"observations":[{"actual":[2147483647,-2147483648],"check":"regression: iadd reaching MAX_VALUE","expected":[2147483647,-2147483648],"passed":true},{"actual":[-4,-4],"check":"idiv truncates toward zero","expected":[-4,-4],"passed":true},{"actual":[-2147483648,2147483647],"check":"idiv MIN_VALUE by -1 overflows to MIN_VALUE","expected":[-2147483648,2147483647],"passed":true},{"actual":[1,-2],"check":"irem takes the sign of the dividend","expected":[-1,2],"passed":false},{"actual":[2,12],"check":"ishl masks the shift count to five bits","expected":[2,12],"passed":true},{"actual":[15,134217727],"check":"iushr is a logical shift with masking","expected":[15,134217727],"passed":true},{"actual":["ArithmeticException","ArithmeticException"],"check":"division by zero","expected":["ArithmeticException","ArithmeticException"],"passed":true},{"actual":[65536,-2,-2147483648,"VerifyError"],"check":"controls: imul wrap, ishr, ineg MIN","expected":[65536,-2,-2147483648,"VerifyError"],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"regression: iadd reaching MAX_VALUE\", \"actual\": [2147483647, -2147483648], \"expected\": [2147483647, -2147483648], \"passed\": true}, {\"check\": \"idiv truncates toward zero\", \"actual\": [-4, -4], \"expected\": [-4, -4], \"passed\": true}, {\"check\": \"idiv MIN_VALUE by -1 overflows to MIN_VALUE\", \"actual\": [-2147483648, 2147483647], \"expected\": [-2147483648, 2147483647], \"passed\": true}, {\"check\": \"irem takes the sign of the dividend\", \"actual\": [1, -2], \"expected\": [-1, 2], \"passed\": false}, {\"check\": \"ishl masks the shift count to five bits\", \"actual\": [2, 12], \"expected\": [2, 12], \"passed\": true}, {\"check\": \"iushr is a logical shift with masking\", \"actual\": [15, 134217727], \"expected\": [15, 134217727], \"passed\": true}, {\"check\": \"division by zero\", \"actual\": [\"ArithmeticException\", \"ArithmeticException\"], \"expected\": [\"ArithmeticException\", \"ArithmeticException\"], \"passed\": true}, {\"check\": \"controls: imul wrap, ishr, ineg MIN\", \"actual\": [65536, -2, -2147483648, \"VerifyError\"], \"expected\": [65536, -2, -2147483648, \"VerifyError\"], \"passed\": true}], \"passed\": false}\n"},"broken":{"elapsed_ms":41.954,"exit_code":1,"observations":[{"actual":[2147483647,-2147483648],"check":"regression: iadd reaching MAX_VALUE","expected":[2147483647,-2147483648],"passed":true},{"actual":[-4,-4],"check":"idiv truncates toward zero","expected":[-4,-4],"passed":true},{"actual":[-2147483648,2147483647],"check":"idiv MIN_VALUE by -1 overflows to MIN_VALUE","expected":[-2147483648,2147483647],"passed":true},{"actual":[2,-1],"check":"irem takes the sign of the dividend","expected":[-1,2],"passed":false},{"actual":[2,12],"check":"ishl masks the shift count to five bits","expected":[2,12],"passed":true},{"actual":[15,134217727],"check":"iushr is a logical shift with masking","expected":[15,134217727],"passed":true},{"actual":["ArithmeticException","ArithmeticException"],"check":"division by zero","expected":["ArithmeticException","ArithmeticException"],"passed":true},{"actual":[65536,-2,-2147483648,"VerifyError"],"check":"controls: imul wrap, ishr, ineg MIN","expected":[65536,-2,-2147483648,"VerifyError"],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"regression: iadd reaching MAX_VALUE\", \"actual\": [2147483647, -2147483648], \"expected\": [2147483647, -2147483648], \"passed\": true}, {\"check\": \"idiv truncates toward zero\", \"actual\": [-4, -4], \"expected\": [-4, -4], \"passed\": true}, {\"check\": \"idiv MIN_VALUE by -1 overflows to MIN_VALUE\", \"actual\": [-2147483648, 2147483647], \"expected\": [-2147483648, 2147483647], \"passed\": true}, {\"check\": \"irem takes the sign of the dividend\", \"actual\": [2, -1], \"expected\": [-1, 2], \"passed\": false}, {\"check\": \"ishl masks the shift count to five bits\", \"actual\": [2, 12], \"expected\": [2, 12], \"passed\": true}, {\"check\": \"iushr is a logical shift with masking\", \"actual\": [15, 134217727], \"expected\": [15, 134217727], \"passed\": true}, {\"check\": \"division by zero\", \"actual\": [\"ArithmeticException\", \"ArithmeticException\"], \"expected\": [\"ArithmeticException\", \"ArithmeticException\"], \"passed\": true}, {\"check\": \"controls: imul wrap, ishr, ineg MIN\", \"actual\": [65536, -2, -2147483648, \"VerifyError\"], \"expected\": [65536, -2, -2147483648, \"VerifyError\"], \"passed\": true}], \"passed\": false}\n"},"fixed":{"elapsed_ms":43.116,"exit_code":0,"observations":[{"actual":[2147483647,-2147483648],"check":"regression: iadd reaching MAX_VALUE","expected":[2147483647,-2147483648],"passed":true},{"actual":[-4,-4],"check":"idiv truncates toward zero","expected":[-4,-4],"passed":true},{"actual":[-2147483648,2147483647],"check":"idiv MIN_VALUE by -1 overflows to MIN_VALUE","expected":[-2147483648,2147483647],"passed":true},{"actual":[-1,2],"check":"irem takes the sign of the dividend","expected":[-1,2],"passed":true},{"actual":[2,12],"check":"ishl masks the shift count to five bits","expected":[2,12],"passed":true},{"actual":[15,134217727],"check":"iushr is a logical shift with masking","expected":[15,134217727],"passed":true},{"actual":["ArithmeticException","ArithmeticException"],"check":"division by zero","expected":["ArithmeticException","ArithmeticException"],"passed":true},{"actual":[65536,-2,-2147483648,"VerifyError"],"check":"controls: imul wrap, ishr, ineg MIN","expected":[65536,-2,-2147483648,"VerifyError"],"passed":true}],"passed":true,"stderr":"","stdout":"{\"observations\": [{\"check\": \"regression: iadd reaching MAX_VALUE\", \"actual\": [2147483647, -2147483648], \"expected\": [2147483647, -2147483648], \"passed\": true}, {\"check\": \"idiv truncates toward zero\", \"actual\": [-4, -4], \"expected\": [-4, -4], \"passed\": true}, {\"check\": \"idiv MIN_VALUE by -1 overflows to MIN_VALUE\", \"actual\": [-2147483648, 2147483647], \"expected\": [-2147483648, 2147483647], \"passed\": true}, {\"check\": \"irem takes the sign of the dividend\", \"actual\": [-1, 2], \"expected\": [-1, 2], \"passed\": true}, {\"check\": \"ishl masks the shift count to five bits\", \"actual\": [2, 12], \"expected\": [2, 12], \"passed\": true}, {\"check\": \"iushr is a logical shift with masking\", \"actual\": [15, 134217727], \"expected\": [15, 134217727], \"passed\": true}, {\"check\": \"division by zero\", \"actual\": [\"ArithmeticException\", \"ArithmeticException\"], \"expected\": [\"ArithmeticException\", \"ArithmeticException\"], \"passed\": true}, {\"check\": \"controls: imul wrap, ishr, ineg MIN\", \"actual\": [65536, -2, -2147483648, \"VerifyError\"], \"expected\": [65536, -2, -2147483648, \"VerifyError\"], \"passed\": true}], \"passed\": true}\n"}},"verified":true,"visibility":"public"}