{"abstract":"lsr reports bit 1 of the original value as carry.","category":"Instruction set emulation","checks":8,"contract":"Input [a, c, ops] with ops asl, lsr, rol, ror, asr on an 8-bit value and a carry bit. asl: C = bit 7, shift left. lsr: C = bit 0, shift right with 0. rol: shift left, bit 0 = old C, new C = old bit 7. ror: shift right, bit 7 = old C, new C = old bit 0. asr: C = bit 0, shift right keeping bit 7. Report [A, C, Z, N] after each op.","contract_signature":"*args","evaluation_group":"w2-instruction-set-emulation-rotate-carry","failed_approach":"Reading bit 1 before the shift is the same wrong bit.","family":"w2-instruction-set-emulation-rotate-carry-logical-shift-carry-source","id":"FA-89806","implementations":{"attempt":{"sha256":"0733fa1a26dc2f2965eaa216176050048545f12e8f0812f61ecff0451aaaec66","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    a, c, ops = args\n    out = []\n    for op in ops:\n        if op == 'asl':\n            c = a >> 7\n            a = (a << 1) & 0xFF\n        elif op == 'lsr':\n            c = (a >> 1) & 1\n            a = a >> 1\n        elif op == 'rol':\n            a, c = ((a << 1) | c) & 0xFF, a >> 7\n        elif op == 'ror':\n            a, c = (a >> 1) | (c << 7), a & 1\n        elif op == 'asr':\n            c = a & 1\n            a = (a >> 1) | (a & 0x80)\n        out.append([a, c, int(a == 0), a >> 7])\n    return out\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]), ('rotate left with carry in', [65, 1, ['rol', 'rol']], [[131, 0, 0, 1], [6, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [4, 1, ['ror', 'ror']], [[130, 0, 0, 1], [65, 0, 0, 0]]), ('arithmetic right shift keeps sign', [197, 0, ['asr', 'asr', 'asr']], [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [5, 0, ['lsr', 'lsr']], [[2, 1, 0, 0], [1, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [86, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0]]), ('rotate left with carry in', [66, 1, ['rol', 'rol']], [[133, 0, 0, 1], [10, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [6, 1, ['ror', 'ror']], [[131, 0, 0, 1], [65, 1, 0, 0]]), ('arithmetic right shift keeps sign', [198, 0, ['asr', 'asr', 'asr']], [[227, 0, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [9, 0, ['lsr', 'lsr']], [[4, 1, 0, 0], [2, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [87, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[175, 0, 0, 1], [87, 1, 0, 0], [171, 1, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0]]), ('rotate left with carry in', [67, 1, ['rol', 'rol']], [[135, 0, 0, 1], [14, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [8, 1, ['ror', 'ror']], [[132, 0, 0, 1], [66, 0, 0, 0]]), ('arithmetic right shift keeps sign', [199, 0, ['asr', 'asr', 'asr']], [[227, 1, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [13, 0, ['lsr', 'lsr']], [[6, 1, 0, 0], [3, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [88, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[177, 0, 0, 1], [88, 1, 0, 0], [172, 0, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1]]), ('rotate left with carry in', [68, 1, ['rol', 'rol']], [[137, 0, 0, 1], [18, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [10, 1, ['ror', 'ror']], [[133, 0, 0, 1], [66, 1, 0, 0]]), ('arithmetic right shift keeps sign', [200, 0, ['asr', 'asr', 'asr']], [[228, 0, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [17, 0, ['lsr', 'lsr']], [[8, 1, 0, 0], [4, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [89, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[179, 0, 0, 1], [89, 1, 0, 0], [172, 1, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1], [64, 1, 0, 0]]), ('rotate left with carry in', [69, 1, ['rol', 'rol']], [[139, 0, 0, 1], [22, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [12, 1, ['ror', 'ror']], [[134, 0, 0, 1], [67, 0, 0, 0]]), ('arithmetic right shift keeps sign', [201, 0, ['asr', 'asr', 'asr']], [[228, 1, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [21, 0, ['lsr', 'lsr']], [[10, 1, 0, 0], [5, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [90, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[181, 0, 0, 1], [90, 1, 0, 0], [173, 0, 0, 1], [214, 1, 0, 1], [172, 1, 0, 1]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"broken":{"sha256":"a06d581565fa268d03aab22a65a64a4370907808c9876017050f26aaf34bb48a","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    a, c, ops = args\n    out = []\n    for op in ops:\n        if op == 'asl':\n            c = a >> 7\n            a = (a << 1) & 0xFF\n        elif op == 'lsr':\n            a = a >> 1\n            c = a & 1\n        elif op == 'rol':\n            a, c = ((a << 1) | c) & 0xFF, a >> 7\n        elif op == 'ror':\n            a, c = (a >> 1) | (c << 7), a & 1\n        elif op == 'asr':\n            c = a & 1\n            a = (a >> 1) | (a & 0x80)\n        out.append([a, c, int(a == 0), a >> 7])\n    return out\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]]), ('rotate left with carry in', [65, 1, ['rol', 'rol']], [[131, 0, 0, 1], [6, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [4, 1, ['ror', 'ror']], [[130, 0, 0, 1], [65, 0, 0, 0]]), ('arithmetic right shift keeps sign', [197, 0, ['asr', 'asr', 'asr']], [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [5, 0, ['lsr', 'lsr']], [[2, 1, 0, 0], [1, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [86, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0]]), ('rotate left with carry in', [66, 1, ['rol', 'rol']], [[133, 0, 0, 1], [10, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [6, 1, ['ror', 'ror']], [[131, 0, 0, 1], [65, 1, 0, 0]]), ('arithmetic right shift keeps sign', [198, 0, ['asr', 'asr', 'asr']], [[227, 0, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [9, 0, ['lsr', 'lsr']], [[4, 1, 0, 0], [2, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [87, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[175, 0, 0, 1], [87, 1, 0, 0], [171, 1, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0]]), ('rotate left with carry in', [67, 1, ['rol', 'rol']], [[135, 0, 0, 1], [14, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [8, 1, ['ror', 'ror']], [[132, 0, 0, 1], [66, 0, 0, 0]]), ('arithmetic right shift keeps sign', [199, 0, ['asr', 'asr', 'asr']], [[227, 1, 0, 1], [241, 1, 0, 1], [248, 1, 0, 1]]), ('logical right shift carry', [13, 0, ['lsr', 'lsr']], [[6, 1, 0, 0], [3, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [88, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[177, 0, 0, 1], [88, 1, 0, 0], [172, 0, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1]]), ('rotate left with carry in', [68, 1, ['rol', 'rol']], [[137, 0, 0, 1], [18, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [10, 1, ['ror', 'ror']], [[133, 0, 0, 1], [66, 1, 0, 0]]), ('arithmetic right shift keeps sign', [200, 0, ['asr', 'asr', 'asr']], [[228, 0, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [17, 0, ['lsr', 'lsr']], [[8, 1, 0, 0], [4, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [89, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[179, 0, 0, 1], [89, 1, 0, 0], [172, 1, 0, 1], [214, 0, 0, 1], [172, 1, 0, 1]])], [('rotate left through carry', [129, 0, ['rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol', 'rol']], [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0], [40, 0, 0, 0], [80, 0, 0, 0], [160, 0, 0, 1], [64, 1, 0, 0]]), ('rotate left with carry in', [69, 1, ['rol', 'rol']], [[139, 0, 0, 1], [22, 1, 0, 0]]), ('rotate right through carry', [1, 1, ['ror', 'ror', 'ror']], [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]]), ('rotate right carry into bit seven', [12, 1, ['ror', 'ror']], [[134, 0, 0, 1], [67, 0, 0, 0]]), ('arithmetic right shift keeps sign', [201, 0, ['asr', 'asr', 'asr']], [[228, 1, 0, 1], [242, 0, 0, 1], [249, 0, 0, 1]]), ('logical right shift carry', [21, 0, ['lsr', 'lsr']], [[10, 1, 0, 0], [5, 0, 0, 0]]), ('shift left carry out', [192, 0, ['asl', 'asl', 'asl']], [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]]), ('mixed sequence', [90, 1, ['rol', 'lsr', 'ror', 'asr', 'asl']], [[181, 0, 0, 1], [90, 1, 0, 0], [173, 0, 0, 1], [214, 1, 0, 1], [172, 1, 0, 1]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"}},"limitations":"A deterministic bounded teaching model of one emulator rule; the instruction semantics are a stipulated contract inspired by common ISAs and are not a claim of cycle-exact or architectural conformance. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.","method":"Deterministic executable model with adversarial boundary fixtures.","provenance":{"created_by":"Failure Map","dependencies":"Python standard library","family":"w2-instruction-set-emulation-rotate-carry-logical-shift-carry-source","generated_at":"2026-09-29T14:51:20.708146+00:00","license":"CC0-1.0","python":"3.12.14","seed":1,"split":"open-access"},"relevance":"Rotate-through-carry instructions implement multi-byte shifts in 8-bit code; emulating them with circular rotates or sequenced updates breaks arithmetic libraries.","root_cause":"Carry is sampled from the already shifted value.","sha256":"c85e43a48661be34eaa9893c00b5c18a78bff4da5ed10f7dbd7bc27cf1091e4f","title":"Logical shift carry taken after shifting · case 01","variant":1,"variant_policy":"Five numbered records share a model and may reuse boundary fixtures.","verified":true,"visibility":"public","verification":{"attempt":{"elapsed_ms":40.068,"exit_code":1,"observations":[{"actual":[[2,1,0,0],[5,0,0,0],[10,0,0,0],[20,0,0,0]],"check":"rotate left through carry","expected":[[2,1,0,0],[5,0,0,0],[10,0,0,0],[20,0,0,0]],"passed":true},{"actual":[[131,0,0,1],[6,1,0,0]],"check":"rotate left with carry in","expected":[[131,0,0,1],[6,1,0,0]],"passed":true},{"actual":[[128,1,0,1],[192,0,0,1],[96,0,0,0]],"check":"rotate right through carry","expected":[[128,1,0,1],[192,0,0,1],[96,0,0,0]],"passed":true},{"actual":[[130,0,0,1],[65,0,0,0]],"check":"rotate right carry into bit seven","expected":[[130,0,0,1],[65,0,0,0]],"passed":true},{"actual":[[226,1,0,1],[241,0,0,1],[248,1,0,1]],"check":"arithmetic right shift keeps sign","expected":[[226,1,0,1],[241,0,0,1],[248,1,0,1]],"passed":true},{"actual":[[2,0,0,0],[1,1,0,0]],"check":"logical right shift carry","expected":[[2,1,0,0],[1,0,0,0]],"passed":false},{"actual":[[128,1,0,1],[0,1,1,0],[0,0,1,0]],"check":"shift left carry out","expected":[[128,1,0,1],[0,1,1,0],[0,0,1,0]],"passed":true},{"actual":[[173,0,0,1],[86,0,0,0],[43,0,0,0],[21,1,0,0],[42,0,0,0]],"check":"mixed sequence","expected":[[173,0,0,1],[86,1,0,0],[171,0,0,1],[213,1,0,1],[170,1,0,1]],"passed":false}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"rotate left through carry\", \"actual\": [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]], \"expected\": [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]], \"passed\": true}, {\"check\": \"rotate left with carry in\", \"actual\": [[131, 0, 0, 1], [6, 1, 0, 0]], \"expected\": [[131, 0, 0, 1], [6, 1, 0, 0]], \"passed\": true}, {\"check\": \"rotate right through carry\", \"actual\": [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]], \"expected\": [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]], \"passed\": true}, {\"check\": \"rotate right carry into bit seven\", \"actual\": [[130, 0, 0, 1], [65, 0, 0, 0]], \"expected\": [[130, 0, 0, 1], [65, 0, 0, 0]], \"passed\": true}, {\"check\": \"arithmetic right shift keeps sign\", \"actual\": [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]], \"expected\": [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]], \"passed\": true}, {\"check\": \"logical right shift carry\", \"actual\": [[2, 0, 0, 0], [1, 1, 0, 0]], \"expected\": [[2, 1, 0, 0], [1, 0, 0, 0]], \"passed\": false}, {\"check\": \"shift left carry out\", \"actual\": [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]], \"expected\": [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]], \"passed\": true}, {\"check\": \"mixed sequence\", \"actual\": [[173, 0, 0, 1], [86, 0, 0, 0], [43, 0, 0, 0], [21, 1, 0, 0], [42, 0, 0, 0]], \"expected\": [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]], \"passed\": false}], \"passed\": false}\n"},"broken":{"elapsed_ms":40.773,"exit_code":1,"observations":[{"actual":[[2,1,0,0],[5,0,0,0],[10,0,0,0],[20,0,0,0]],"check":"rotate left through carry","expected":[[2,1,0,0],[5,0,0,0],[10,0,0,0],[20,0,0,0]],"passed":true},{"actual":[[131,0,0,1],[6,1,0,0]],"check":"rotate left with carry in","expected":[[131,0,0,1],[6,1,0,0]],"passed":true},{"actual":[[128,1,0,1],[192,0,0,1],[96,0,0,0]],"check":"rotate right through carry","expected":[[128,1,0,1],[192,0,0,1],[96,0,0,0]],"passed":true},{"actual":[[130,0,0,1],[65,0,0,0]],"check":"rotate right carry into bit seven","expected":[[130,0,0,1],[65,0,0,0]],"passed":true},{"actual":[[226,1,0,1],[241,0,0,1],[248,1,0,1]],"check":"arithmetic right shift keeps sign","expected":[[226,1,0,1],[241,0,0,1],[248,1,0,1]],"passed":true},{"actual":[[2,0,0,0],[1,1,0,0]],"check":"logical right shift carry","expected":[[2,1,0,0],[1,0,0,0]],"passed":false},{"actual":[[128,1,0,1],[0,1,1,0],[0,0,1,0]],"check":"shift left carry out","expected":[[128,1,0,1],[0,1,1,0],[0,0,1,0]],"passed":true},{"actual":[[173,0,0,1],[86,0,0,0],[43,0,0,0],[21,1,0,0],[42,0,0,0]],"check":"mixed sequence","expected":[[173,0,0,1],[86,1,0,0],[171,0,0,1],[213,1,0,1],[170,1,0,1]],"passed":false}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"rotate left through carry\", \"actual\": [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]], \"expected\": [[2, 1, 0, 0], [5, 0, 0, 0], [10, 0, 0, 0], [20, 0, 0, 0]], \"passed\": true}, {\"check\": \"rotate left with carry in\", \"actual\": [[131, 0, 0, 1], [6, 1, 0, 0]], \"expected\": [[131, 0, 0, 1], [6, 1, 0, 0]], \"passed\": true}, {\"check\": \"rotate right through carry\", \"actual\": [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]], \"expected\": [[128, 1, 0, 1], [192, 0, 0, 1], [96, 0, 0, 0]], \"passed\": true}, {\"check\": \"rotate right carry into bit seven\", \"actual\": [[130, 0, 0, 1], [65, 0, 0, 0]], \"expected\": [[130, 0, 0, 1], [65, 0, 0, 0]], \"passed\": true}, {\"check\": \"arithmetic right shift keeps sign\", \"actual\": [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]], \"expected\": [[226, 1, 0, 1], [241, 0, 0, 1], [248, 1, 0, 1]], \"passed\": true}, {\"check\": \"logical right shift carry\", \"actual\": [[2, 0, 0, 0], [1, 1, 0, 0]], \"expected\": [[2, 1, 0, 0], [1, 0, 0, 0]], \"passed\": false}, {\"check\": \"shift left carry out\", \"actual\": [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]], \"expected\": [[128, 1, 0, 1], [0, 1, 1, 0], [0, 0, 1, 0]], \"passed\": true}, {\"check\": \"mixed sequence\", \"actual\": [[173, 0, 0, 1], [86, 0, 0, 0], [43, 0, 0, 0], [21, 1, 0, 0], [42, 0, 0, 0]], \"expected\": [[173, 0, 0, 1], [86, 1, 0, 0], [171, 0, 0, 1], [213, 1, 0, 1], [170, 1, 0, 1]], \"passed\": false}], \"passed\": false}\n"}},"member_only":{"stages":["fixed"],"fields":["implementations.fixed","verification.fixed","harness","repair"],"note":"The verified repair, its recorded checks, the repair description, and the scoring harness are available to members."}}