{"abstract":"With vectored mode enabled, traps jump to an odd address.","category":"Instruction set emulation","checks":8,"contract":"Input [pc, priv, mie, mtvec, events]; MPIE, MPP, mcause, mepc start 0. step: pc += 4. ecall: exception cause 8 + priv (U 8, S 9, M 11). illegal: cause 2. irq k: interrupt cause 2^31 | k, taken only if priv < 3 or MIE. Trap: mepc = pc, mcause = cause, MPIE = MIE, MIE = 0, MPP = priv, priv = 3, pc = mtvec base (mtvec & ~3), plus 4*k for interrupts when mtvec mode (low 2 bits) is 1. mret: MIE = MPIE, MPIE = 1, priv = MPP, MPP = 0, pc = mepc. Return [pc, priv, MIE, MPIE, MPP, mcause, mepc] after each event.","evaluation_group":"w2-instruction-set-emulation-trap-entry","failed_approach":"Masking only bit 0 leaves bit 1 in the base.","family":"w2-instruction-set-emulation-trap-entry-trap-vector-base","id":"FA-89776","implementations":{"attempt":{"sha256":"a1f97b319c3df47f0f26f367cd2a007a943956f6f98b2cd4d05f2680055ef79c","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    pc, priv, mie, mtvec, events = args\n    mpie = mpp = mcause = mepc = 0\n    log = []\n    for ev in events:\n        kind = ev[0]\n        trap = None\n        if kind == 'step':\n            pc += 4\n        elif kind == 'ecall':\n            trap = 8 + priv\n        elif kind == 'illegal':\n            trap = 2\n        elif kind == 'irq':\n            if priv < 3 or mie:\n                trap = (1 << 31) | ev[1]\n        elif kind == 'mret':\n            mie = mpie\n            mpie = 1\n            priv = mpp\n            mpp = 0\n            pc = mepc\n        if trap is not None:\n            mepc = pc\n            mcause = trap\n            mpie = mie\n            mie = 0\n            mpp = priv\n            priv = 3\n            base = mtvec & ~1\n            pc = base + 4 * (trap & 0x7FFFFFFF) if (mtvec & 3) == 1 and trap >> 31 else base\n        log.append([pc, priv, mie, mpie, mpp, mcause, mepc])\n    return log\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('user ecall and return', [1028, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4354, [['ecall'], ['mret']]], [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1032, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1036, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1036], [4100, 3, 0, 1, 0, 8, 1036], [1036, 0, 1, 1, 0, 8, 1036]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4610, [['ecall'], ['mret']]], [[4608, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1036, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1040, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1040], [4100, 3, 0, 1, 0, 8, 1040], [1040, 0, 1, 1, 0, 8, 1040]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4866, [['ecall'], ['mret']]], [[4864, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1040, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1044, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1044], [4100, 3, 0, 1, 0, 8, 1044], [1044, 0, 1, 1, 0, 8, 1044]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5122, [['ecall'], ['mret']]], [[5120, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1044, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1048, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1048], [4100, 3, 0, 1, 0, 8, 1048], [1048, 0, 1, 1, 0, 8, 1048]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5378, [['ecall'], ['mret']]], [[5376, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096], [4116, 0, 1, 1, 0, 2, 4096]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"broken":{"sha256":"cea69013ab666d7a6c3a2476be7b3b9a69f9eb94bbdf6af58d27f71f030f12a6","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    pc, priv, mie, mtvec, events = args\n    mpie = mpp = mcause = mepc = 0\n    log = []\n    for ev in events:\n        kind = ev[0]\n        trap = None\n        if kind == 'step':\n            pc += 4\n        elif kind == 'ecall':\n            trap = 8 + priv\n        elif kind == 'illegal':\n            trap = 2\n        elif kind == 'irq':\n            if priv < 3 or mie:\n                trap = (1 << 31) | ev[1]\n        elif kind == 'mret':\n            mie = mpie\n            mpie = 1\n            priv = mpp\n            mpp = 0\n            pc = mepc\n        if trap is not None:\n            mepc = pc\n            mcause = trap\n            mpie = mie\n            mie = 0\n            mpp = priv\n            priv = 3\n            base = mtvec\n            pc = base + 4 * (trap & 0x7FFFFFFF) if (mtvec & 3) == 1 and trap >> 31 else base\n        log.append([pc, priv, mie, mpie, mpp, mcause, mepc])\n    return log\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('user ecall and return', [1028, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4354, [['ecall'], ['mret']]], [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1032, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1036, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1036], [4100, 3, 0, 1, 0, 8, 1036], [1036, 0, 1, 1, 0, 8, 1036]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4610, [['ecall'], ['mret']]], [[4608, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1036, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1040, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1040], [4100, 3, 0, 1, 0, 8, 1040], [1040, 0, 1, 1, 0, 8, 1040]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4866, [['ecall'], ['mret']]], [[4864, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1040, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1044, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1044], [4100, 3, 0, 1, 0, 8, 1044], [1044, 0, 1, 1, 0, 8, 1044]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5122, [['ecall'], ['mret']]], [[5120, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1044, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1048, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1048], [4100, 3, 0, 1, 0, 8, 1048], [1048, 0, 1, 1, 0, 8, 1048]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5378, [['ecall'], ['mret']]], [[5376, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096], [4116, 0, 1, 1, 0, 2, 4096]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"fixed":{"sha256":"0b2a873f8a03df16cb855a93f29fc263ffe64e9c097843541279d90834d43f1d","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    pc, priv, mie, mtvec, events = args\n    mpie = mpp = mcause = mepc = 0\n    log = []\n    for ev in events:\n        kind = ev[0]\n        trap = None\n        if kind == 'step':\n            pc += 4\n        elif kind == 'ecall':\n            trap = 8 + priv\n        elif kind == 'illegal':\n            trap = 2\n        elif kind == 'irq':\n            if priv < 3 or mie:\n                trap = (1 << 31) | ev[1]\n        elif kind == 'mret':\n            mie = mpie\n            mpie = 1\n            priv = mpp\n            mpp = 0\n            pc = mepc\n        if trap is not None:\n            mepc = pc\n            mcause = trap\n            mpie = mie\n            mie = 0\n            mpp = priv\n            priv = 3\n            base = mtvec & ~3\n            pc = base + 4 * (trap & 0x7FFFFFFF) if (mtvec & 3) == 1 and trap >> 31 else base\n        log.append([pc, priv, mie, mpie, mpp, mcause, mepc])\n    return log\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('user ecall and return', [1028, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4354, [['ecall'], ['mret']]], [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1032, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1036, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1036], [4100, 3, 0, 1, 0, 8, 1036], [1036, 0, 1, 1, 0, 8, 1036]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4610, [['ecall'], ['mret']]], [[4608, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1036, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1040, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1040], [4100, 3, 0, 1, 0, 8, 1040], [1040, 0, 1, 1, 0, 8, 1040]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 4866, [['ecall'], ['mret']]], [[4864, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1040, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1044, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1044], [4100, 3, 0, 1, 0, 8, 1044], [1044, 0, 1, 1, 0, 8, 1044]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 11]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4140, 3, 0, 0, 0, 2147483659, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5122, [['ecall'], ['mret']]], [[5120, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096]])], [('user ecall and return', [1044, 0, 1, 4096, [['step'], ['ecall'], ['step'], ['mret']]], [[1048, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1048], [4100, 3, 0, 1, 0, 8, 1048], [1048, 0, 1, 1, 0, 8, 1048]]), ('supervisor and machine ecall', [1024, 1, 0, 4096, [['ecall'], ['ecall'], ['mret'], ['mret']]], [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]]), ('supervisor interrupt with mie clear', [1280, 1, 0, 4097, [['irq', 7], ['mret'], ['step']]], [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]]), ('machine interrupt masked then enabled', [1536, 3, 0, 4097, [['irq', 3], ['step'], ['mret'], ['irq', 10]]], [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]]), ('machine interrupt enabled saves mie', [1792, 3, 1, 8192, [['irq', 7], ['mret'], ['step']]], [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]]), ('vectored mode exceptions go to base', [2048, 0, 1, 12289, [['illegal'], ['mret'], ['ecall']]], [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]]), ('reserved mode bits masked', [2560, 1, 1, 5378, [['ecall'], ['mret']]], [[5376, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]]), ('nested trap overwrites mpp', [2304, 0, 1, 4096, [['ecall'], ['illegal'], ['mret'], ['mret'], ['step'], ['step'], ['step'], ['step'], ['step']]], [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096], [4104, 0, 1, 1, 0, 2, 4096], [4108, 0, 1, 1, 0, 2, 4096], [4112, 0, 1, 1, 0, 2, 4096], [4116, 0, 1, 1, 0, 2, 4096]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"}},"limitations":"A deterministic bounded teaching model of one emulator rule; the instruction semantics are a stipulated contract inspired by common ISAs and are not a claim of cycle-exact or architectural conformance. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.","method":"Deterministic executable model with adversarial boundary fixtures.","provenance":{"created_by":"Failure Map","dependencies":"Python standard library","family":"w2-instruction-set-emulation-trap-entry-trap-vector-base","generated_at":"2026-09-29T14:51:20.581040+00:00","license":"CC0-1.0","python":"3.12.14","seed":1,"split":"open-access"},"relevance":"Trap and return sequencing defines how emulated operating systems handle syscalls and interrupts; one misordered status update corrupts the interrupt enable state.","repair":"Mask the low two mode bits from mtvec.","root_cause":"The mode field is not masked off the trap vector base.","sha256":"e3c8ccca5682a76cd450d6c81154669ea772701a05cfc3bf7538bd8f9db98560","title":"Trap vector includes the mode bits · case 01","variant":1,"variant_policy":"Five numbered records share a model and may reuse boundary fixtures.","verification":{"attempt":{"elapsed_ms":40.38,"exit_code":1,"observations":[{"actual":[[1032,0,1,0,0,0,0],[4096,3,0,1,0,8,1032],[4100,3,0,1,0,8,1032],[1032,0,1,1,0,8,1032]],"check":"user ecall and return","expected":[[1032,0,1,0,0,0,0],[4096,3,0,1,0,8,1032],[4100,3,0,1,0,8,1032],[1032,0,1,1,0,8,1032]],"passed":true},{"actual":[[4096,3,0,0,1,9,1024],[4096,3,0,0,3,11,4096],[4096,3,0,1,0,11,4096],[4096,0,1,1,0,11,4096]],"check":"supervisor and machine ecall","expected":[[4096,3,0,0,1,9,1024],[4096,3,0,0,3,11,4096],[4096,3,0,1,0,11,4096],[4096,0,1,1,0,11,4096]],"passed":true},{"actual":[[4124,3,0,0,1,2147483655,1280],[1280,1,0,1,0,2147483655,1280],[1284,1,0,1,0,2147483655,1280]],"check":"supervisor interrupt with mie clear","expected":[[4124,3,0,0,1,2147483655,1280],[1280,1,0,1,0,2147483655,1280],[1284,1,0,1,0,2147483655,1280]],"passed":true},{"actual":[[1536,3,0,0,0,0,0],[1540,3,0,0,0,0,0],[0,0,0,1,0,0,0],[4136,3,0,0,0,2147483658,0]],"check":"machine interrupt masked then enabled","expected":[[1536,3,0,0,0,0,0],[1540,3,0,0,0,0,0],[0,0,0,1,0,0,0],[4136,3,0,0,0,2147483658,0]],"passed":true},{"actual":[[8192,3,0,1,3,2147483655,1792],[1792,3,1,1,0,2147483655,1792],[1796,3,1,1,0,2147483655,1792]],"check":"machine interrupt enabled saves mie","expected":[[8192,3,0,1,3,2147483655,1792],[1792,3,1,1,0,2147483655,1792],[1796,3,1,1,0,2147483655,1792]],"passed":true},{"actual":[[12288,3,0,1,0,2,2048],[2048,0,1,1,0,2,2048],[12288,3,0,1,0,8,2048]],"check":"vectored mode exceptions go to base","expected":[[12288,3,0,1,0,2,2048],[2048,0,1,1,0,2,2048],[12288,3,0,1,0,8,2048]],"passed":true},{"actual":[[4354,3,0,1,1,9,2560],[2560,1,1,1,0,9,2560]],"check":"reserved mode bits masked","expected":[[4352,3,0,1,1,9,2560],[2560,1,1,1,0,9,2560]],"passed":false},{"actual":[[4096,3,0,1,0,8,2304],[4096,3,0,0,3,2,4096],[4096,3,0,1,0,2,4096],[4096,0,1,1,0,2,4096],[4100,0,1,1,0,2,4096]],"check":"nested trap overwrites mpp","expected":[[4096,3,0,1,0,8,2304],[4096,3,0,0,3,2,4096],[4096,3,0,1,0,2,4096],[4096,0,1,1,0,2,4096],[4100,0,1,1,0,2,4096]],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"user ecall and return\", \"actual\": [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]], \"expected\": [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]], \"passed\": true}, {\"check\": \"supervisor and machine ecall\", \"actual\": [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]], \"expected\": [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]], \"passed\": true}, {\"check\": \"supervisor interrupt with mie clear\", \"actual\": [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]], \"expected\": [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]], \"passed\": true}, {\"check\": \"machine interrupt masked then enabled\", \"actual\": [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]], \"expected\": [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]], \"passed\": true}, {\"check\": \"machine interrupt enabled saves mie\", \"actual\": [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]], \"expected\": [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]], \"passed\": true}, {\"check\": \"vectored mode exceptions go to base\", \"actual\": [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]], \"expected\": [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]], \"passed\": true}, {\"check\": \"reserved mode bits masked\", \"actual\": [[4354, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]], \"expected\": [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]], \"passed\": false}, {\"check\": \"nested trap overwrites mpp\", \"actual\": [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]], \"expected\": [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]], \"passed\": true}], \"passed\": false}\n"},"broken":{"elapsed_ms":41.178,"exit_code":1,"observations":[{"actual":[[1032,0,1,0,0,0,0],[4096,3,0,1,0,8,1032],[4100,3,0,1,0,8,1032],[1032,0,1,1,0,8,1032]],"check":"user ecall and return","expected":[[1032,0,1,0,0,0,0],[4096,3,0,1,0,8,1032],[4100,3,0,1,0,8,1032],[1032,0,1,1,0,8,1032]],"passed":true},{"actual":[[4096,3,0,0,1,9,1024],[4096,3,0,0,3,11,4096],[4096,3,0,1,0,11,4096],[4096,0,1,1,0,11,4096]],"check":"supervisor and machine ecall","expected":[[4096,3,0,0,1,9,1024],[4096,3,0,0,3,11,4096],[4096,3,0,1,0,11,4096],[4096,0,1,1,0,11,4096]],"passed":true},{"actual":[[4125,3,0,0,1,2147483655,1280],[1280,1,0,1,0,2147483655,1280],[1284,1,0,1,0,2147483655,1280]],"check":"supervisor interrupt with mie clear","expected":[[4124,3,0,0,1,2147483655,1280],[1280,1,0,1,0,2147483655,1280],[1284,1,0,1,0,2147483655,1280]],"passed":false},{"actual":[[1536,3,0,0,0,0,0],[1540,3,0,0,0,0,0],[0,0,0,1,0,0,0],[4137,3,0,0,0,2147483658,0]],"check":"machine interrupt masked then enabled","expected":[[1536,3,0,0,0,0,0],[1540,3,0,0,0,0,0],[0,0,0,1,0,0,0],[4136,3,0,0,0,2147483658,0]],"passed":false},{"actual":[[8192,3,0,1,3,2147483655,1792],[1792,3,1,1,0,2147483655,1792],[1796,3,1,1,0,2147483655,1792]],"check":"machine interrupt enabled saves mie","expected":[[8192,3,0,1,3,2147483655,1792],[1792,3,1,1,0,2147483655,1792],[1796,3,1,1,0,2147483655,1792]],"passed":true},{"actual":[[12289,3,0,1,0,2,2048],[2048,0,1,1,0,2,2048],[12289,3,0,1,0,8,2048]],"check":"vectored mode exceptions go to base","expected":[[12288,3,0,1,0,2,2048],[2048,0,1,1,0,2,2048],[12288,3,0,1,0,8,2048]],"passed":false},{"actual":[[4354,3,0,1,1,9,2560],[2560,1,1,1,0,9,2560]],"check":"reserved mode bits masked","expected":[[4352,3,0,1,1,9,2560],[2560,1,1,1,0,9,2560]],"passed":false},{"actual":[[4096,3,0,1,0,8,2304],[4096,3,0,0,3,2,4096],[4096,3,0,1,0,2,4096],[4096,0,1,1,0,2,4096],[4100,0,1,1,0,2,4096]],"check":"nested trap overwrites mpp","expected":[[4096,3,0,1,0,8,2304],[4096,3,0,0,3,2,4096],[4096,3,0,1,0,2,4096],[4096,0,1,1,0,2,4096],[4100,0,1,1,0,2,4096]],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"user ecall and return\", \"actual\": [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]], \"expected\": [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]], \"passed\": true}, {\"check\": \"supervisor and machine ecall\", \"actual\": [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]], \"expected\": [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]], \"passed\": true}, {\"check\": \"supervisor interrupt with mie clear\", \"actual\": [[4125, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]], \"expected\": [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]], \"passed\": false}, {\"check\": \"machine interrupt masked then enabled\", \"actual\": [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4137, 3, 0, 0, 0, 2147483658, 0]], \"expected\": [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]], \"passed\": false}, {\"check\": \"machine interrupt enabled saves mie\", \"actual\": [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]], \"expected\": [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]], \"passed\": true}, {\"check\": \"vectored mode exceptions go to base\", \"actual\": [[12289, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12289, 3, 0, 1, 0, 8, 2048]], \"expected\": [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]], \"passed\": false}, {\"check\": \"reserved mode bits masked\", \"actual\": [[4354, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]], \"expected\": [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]], \"passed\": false}, {\"check\": \"nested trap overwrites mpp\", \"actual\": [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]], \"expected\": [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]], \"passed\": true}], \"passed\": false}\n"},"fixed":{"elapsed_ms":43.76,"exit_code":0,"observations":[{"actual":[[1032,0,1,0,0,0,0],[4096,3,0,1,0,8,1032],[4100,3,0,1,0,8,1032],[1032,0,1,1,0,8,1032]],"check":"user ecall and return","expected":[[1032,0,1,0,0,0,0],[4096,3,0,1,0,8,1032],[4100,3,0,1,0,8,1032],[1032,0,1,1,0,8,1032]],"passed":true},{"actual":[[4096,3,0,0,1,9,1024],[4096,3,0,0,3,11,4096],[4096,3,0,1,0,11,4096],[4096,0,1,1,0,11,4096]],"check":"supervisor and machine ecall","expected":[[4096,3,0,0,1,9,1024],[4096,3,0,0,3,11,4096],[4096,3,0,1,0,11,4096],[4096,0,1,1,0,11,4096]],"passed":true},{"actual":[[4124,3,0,0,1,2147483655,1280],[1280,1,0,1,0,2147483655,1280],[1284,1,0,1,0,2147483655,1280]],"check":"supervisor interrupt with mie clear","expected":[[4124,3,0,0,1,2147483655,1280],[1280,1,0,1,0,2147483655,1280],[1284,1,0,1,0,2147483655,1280]],"passed":true},{"actual":[[1536,3,0,0,0,0,0],[1540,3,0,0,0,0,0],[0,0,0,1,0,0,0],[4136,3,0,0,0,2147483658,0]],"check":"machine interrupt masked then enabled","expected":[[1536,3,0,0,0,0,0],[1540,3,0,0,0,0,0],[0,0,0,1,0,0,0],[4136,3,0,0,0,2147483658,0]],"passed":true},{"actual":[[8192,3,0,1,3,2147483655,1792],[1792,3,1,1,0,2147483655,1792],[1796,3,1,1,0,2147483655,1792]],"check":"machine interrupt enabled saves mie","expected":[[8192,3,0,1,3,2147483655,1792],[1792,3,1,1,0,2147483655,1792],[1796,3,1,1,0,2147483655,1792]],"passed":true},{"actual":[[12288,3,0,1,0,2,2048],[2048,0,1,1,0,2,2048],[12288,3,0,1,0,8,2048]],"check":"vectored mode exceptions go to base","expected":[[12288,3,0,1,0,2,2048],[2048,0,1,1,0,2,2048],[12288,3,0,1,0,8,2048]],"passed":true},{"actual":[[4352,3,0,1,1,9,2560],[2560,1,1,1,0,9,2560]],"check":"reserved mode bits masked","expected":[[4352,3,0,1,1,9,2560],[2560,1,1,1,0,9,2560]],"passed":true},{"actual":[[4096,3,0,1,0,8,2304],[4096,3,0,0,3,2,4096],[4096,3,0,1,0,2,4096],[4096,0,1,1,0,2,4096],[4100,0,1,1,0,2,4096]],"check":"nested trap overwrites mpp","expected":[[4096,3,0,1,0,8,2304],[4096,3,0,0,3,2,4096],[4096,3,0,1,0,2,4096],[4096,0,1,1,0,2,4096],[4100,0,1,1,0,2,4096]],"passed":true}],"passed":true,"stderr":"","stdout":"{\"observations\": [{\"check\": \"user ecall and return\", \"actual\": [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]], \"expected\": [[1032, 0, 1, 0, 0, 0, 0], [4096, 3, 0, 1, 0, 8, 1032], [4100, 3, 0, 1, 0, 8, 1032], [1032, 0, 1, 1, 0, 8, 1032]], \"passed\": true}, {\"check\": \"supervisor and machine ecall\", \"actual\": [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]], \"expected\": [[4096, 3, 0, 0, 1, 9, 1024], [4096, 3, 0, 0, 3, 11, 4096], [4096, 3, 0, 1, 0, 11, 4096], [4096, 0, 1, 1, 0, 11, 4096]], \"passed\": true}, {\"check\": \"supervisor interrupt with mie clear\", \"actual\": [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]], \"expected\": [[4124, 3, 0, 0, 1, 2147483655, 1280], [1280, 1, 0, 1, 0, 2147483655, 1280], [1284, 1, 0, 1, 0, 2147483655, 1280]], \"passed\": true}, {\"check\": \"machine interrupt masked then enabled\", \"actual\": [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]], \"expected\": [[1536, 3, 0, 0, 0, 0, 0], [1540, 3, 0, 0, 0, 0, 0], [0, 0, 0, 1, 0, 0, 0], [4136, 3, 0, 0, 0, 2147483658, 0]], \"passed\": true}, {\"check\": \"machine interrupt enabled saves mie\", \"actual\": [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]], \"expected\": [[8192, 3, 0, 1, 3, 2147483655, 1792], [1792, 3, 1, 1, 0, 2147483655, 1792], [1796, 3, 1, 1, 0, 2147483655, 1792]], \"passed\": true}, {\"check\": \"vectored mode exceptions go to base\", \"actual\": [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]], \"expected\": [[12288, 3, 0, 1, 0, 2, 2048], [2048, 0, 1, 1, 0, 2, 2048], [12288, 3, 0, 1, 0, 8, 2048]], \"passed\": true}, {\"check\": \"reserved mode bits masked\", \"actual\": [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]], \"expected\": [[4352, 3, 0, 1, 1, 9, 2560], [2560, 1, 1, 1, 0, 9, 2560]], \"passed\": true}, {\"check\": \"nested trap overwrites mpp\", \"actual\": [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]], \"expected\": [[4096, 3, 0, 1, 0, 8, 2304], [4096, 3, 0, 0, 3, 2, 4096], [4096, 3, 0, 1, 0, 2, 4096], [4096, 0, 1, 1, 0, 2, 4096], [4100, 0, 1, 1, 0, 2, 4096]], \"passed\": true}], \"passed\": true}\n"}},"verified":true,"visibility":"public"}