{"abstract":"csrrs with rs1=x0 on a read-only counter traps, and a set with a zero-valued nonzero register does not.","category":"Instruction set emulation","checks":11,"contract":"Input [priv, csr, op, rs1, value, csrs] with priv 0 (U), 1 (S) or 3 (M) and csrs mapping decimal-string CSR numbers to values. Unknown CSR -> 'illegal'. Bits 9:8 of the CSR number give the lowest privilege allowed; bits 11:10 equal to 3 mark it read-only. csrrw/csrrwi always write; csrrs/csrrc/csrrsi/csrrci write only when the rs1 field (register index, or the 5-bit immediate for i-forms) is nonzero. Writing a read-only CSR -> 'illegal'. Operand: the register value, or the rs1 field itself for i-forms. New value: rw -> operand, rs -> old | operand, rc -> old & ~operand. Return ['ok', old, new (old if no write)].","evaluation_group":"w2-instruction-set-emulation-csr-access","failed_approach":"Requiring both a nonzero field and value misses writes of zero through a real register.","family":"w2-instruction-set-emulation-csr-access-write-intent-source","id":"FA-89736","implementations":{"attempt":{"sha256":"d96c7c5b45b4518c42a7f3039364d01ae6267851d517c9d71d4bc7bc5d3d39ac","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    priv, csr, op, rs1, val, csrs = args\n    if str(csr) not in csrs:\n        return 'illegal'\n    ro = (csr >> 10) & 3 == 3\n    need = (csr >> 8) & 3\n    if priv < need:\n        return 'illegal'\n    imm = op.endswith('i')\n    v = rs1 if imm else val\n    writes = op in ('csrrw', 'csrrwi') or (rs1 != 0 and v != 0)\n    if ro and writes:\n        return 'illegal'\n    old = csrs[str(csr)]\n    base = op[:5]\n    if base == 'csrrw': new = v\n    elif base == 'csrrs': new = old | v\n    else: new = old & ~v & 0xFFFFFFFF\n    return ['ok', old, new if writes else old]\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('machine writes machine csr', [3, 768, 'csrrw', 5, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 9]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 124, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 100, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 4, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 4]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 292, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 10, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 10]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 125, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 101, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 5, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 5]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 293, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 11, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 11]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 126, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 102, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 6]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 294, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 12, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 12]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 127, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 103, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 7, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 7]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 295, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 13, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 13]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 128, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 104, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 8, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 8]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 296, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"broken":{"sha256":"723b6cf0061335f7e4d3135a25232cb326c8f911ac6df8a859773b725372b319","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    priv, csr, op, rs1, val, csrs = args\n    if str(csr) not in csrs:\n        return 'illegal'\n    ro = (csr >> 10) & 3 == 3\n    need = (csr >> 8) & 3\n    if priv < need:\n        return 'illegal'\n    imm = op.endswith('i')\n    v = rs1 if imm else val\n    writes = op in ('csrrw', 'csrrwi') or v != 0\n    if ro and writes:\n        return 'illegal'\n    old = csrs[str(csr)]\n    base = op[:5]\n    if base == 'csrrw': new = v\n    elif base == 'csrrs': new = old | v\n    else: new = old & ~v & 0xFFFFFFFF\n    return ['ok', old, new if writes else old]\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('machine writes machine csr', [3, 768, 'csrrw', 5, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 9]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 124, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 100, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 4, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 4]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 292, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 10, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 10]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 125, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 101, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 5, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 5]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 293, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 11, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 11]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 126, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 102, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 6]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 294, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 12, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 12]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 127, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 103, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 7, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 7]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 295, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 13, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 13]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 128, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 104, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 8, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 8]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 296, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"fixed":{"sha256":"2571a01f6b2f110db846c098e60a1678b738deceec272c1f8f4e9b6b028df191","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    priv, csr, op, rs1, val, csrs = args\n    if str(csr) not in csrs:\n        return 'illegal'\n    ro = (csr >> 10) & 3 == 3\n    need = (csr >> 8) & 3\n    if priv < need:\n        return 'illegal'\n    imm = op.endswith('i')\n    v = rs1 if imm else val\n    writes = op in ('csrrw', 'csrrwi') or rs1 != 0\n    if ro and writes:\n        return 'illegal'\n    old = csrs[str(csr)]\n    base = op[:5]\n    if base == 'csrrw': new = v\n    elif base == 'csrrs': new = old | v\n    else: new = old & ~v & 0xFFFFFFFF\n    return ['ok', old, new if writes else old]\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('machine writes machine csr', [3, 768, 'csrrw', 5, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 9]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 124, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 100, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 4, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 4]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 292, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 10, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 10]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 125, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 101, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 5, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 5]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 293, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 11, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 11]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 126, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 102, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 6]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 294, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 12, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 12]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 127, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 103, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 7, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 7]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 295, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')], [('machine writes machine csr', [3, 768, 'csrrw', 5, 13, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 6144, 13]), ('user reads read-only counter', [0, 3072, 'csrrs', 0, 128, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 2457, 2457]), ('user set-bits with nonzero rs1 on read-only', [0, 3072, 'csrrs', 3, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('supervisor touches machine csr', [1, 768, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('immediate write to read-only hart id', [3, 3860, 'csrrwi', 0, 9, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('clear bits in user csr', [0, 1, 'csrrc', 2, 6, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 1]), ('set bits immediate form', [0, 1, 'csrrsi', 2, 104, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 5, 7]), ('custom machine read-write csr', [3, 1985, 'csrrw', 1, 8, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 7, 8]), ('machine counter is writable', [3, 2816, 'csrrwi', 4, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], ['ok', 50, 4]), ('user reads supervisor csr', [0, 256, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal'), ('missing csr', [3, 296, 'csrrs', 0, 0, {'768': 6144, '3860': 17, '256': 34, '3072': 2457, '1': 5, '1985': 7, '2816': 50}], 'illegal')]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"}},"limitations":"A deterministic bounded teaching model of one emulator rule; the instruction semantics are a stipulated contract inspired by common ISAs and are not a claim of cycle-exact or architectural conformance. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.","method":"Deterministic executable model with adversarial boundary fixtures.","provenance":{"created_by":"Failure Map","dependencies":"Python standard library","family":"w2-instruction-set-emulation-csr-access-write-intent-source","generated_at":"2026-09-29T14:51:20.058419+00:00","license":"CC0-1.0","python":"3.12.14","seed":1,"split":"open-access"},"relevance":"Privileged-architecture emulation must reject illegal CSR accesses exactly, since operating systems probe CSRs and rely on traps.","repair":"Decide write intent from the rs1 field (register index or immediate), not the value.","root_cause":"Whether a set/clear writes is decided from the operand value instead of the rs1 field.","sha256":"10bf8ca83a9f2a5a821442b17a37c2774244ecafac686a8c292f99dee1a8af72","title":"Write intent derived from the register value · case 01","variant":1,"variant_policy":"Five numbered records share a model and may reuse boundary fixtures.","verification":{"attempt":{"elapsed_ms":41.353,"exit_code":1,"observations":[{"actual":["ok",6144,9],"check":"machine writes machine csr","expected":["ok",6144,9],"passed":true},{"actual":["ok",2457,2457],"check":"user reads read-only counter","expected":["ok",2457,2457],"passed":true},{"actual":["ok",2457,2457],"check":"user set-bits with nonzero rs1 on read-only","expected":"illegal","passed":false},{"actual":"illegal","check":"supervisor touches machine csr","expected":"illegal","passed":true},{"actual":"illegal","check":"immediate write to read-only hart id","expected":"illegal","passed":true},{"actual":["ok",5,1],"check":"clear bits in user csr","expected":["ok",5,1],"passed":true},{"actual":["ok",5,7],"check":"set bits immediate form","expected":["ok",5,7],"passed":true},{"actual":["ok",7,4],"check":"custom machine read-write csr","expected":["ok",7,4],"passed":true},{"actual":["ok",50,4],"check":"machine counter is writable","expected":["ok",50,4],"passed":true},{"actual":"illegal","check":"user reads supervisor csr","expected":"illegal","passed":true},{"actual":"illegal","check":"missing csr","expected":"illegal","passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"machine writes machine csr\", \"actual\": [\"ok\", 6144, 9], \"expected\": [\"ok\", 6144, 9], \"passed\": true}, {\"check\": \"user reads read-only counter\", \"actual\": [\"ok\", 2457, 2457], \"expected\": [\"ok\", 2457, 2457], \"passed\": true}, {\"check\": \"user set-bits with nonzero rs1 on read-only\", \"actual\": [\"ok\", 2457, 2457], \"expected\": \"illegal\", \"passed\": false}, {\"check\": \"supervisor touches machine csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"immediate write to read-only hart id\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"clear bits in user csr\", \"actual\": [\"ok\", 5, 1], \"expected\": [\"ok\", 5, 1], \"passed\": true}, {\"check\": \"set bits immediate form\", \"actual\": [\"ok\", 5, 7], \"expected\": [\"ok\", 5, 7], \"passed\": true}, {\"check\": \"custom machine read-write csr\", \"actual\": [\"ok\", 7, 4], \"expected\": [\"ok\", 7, 4], \"passed\": true}, {\"check\": \"machine counter is writable\", \"actual\": [\"ok\", 50, 4], \"expected\": [\"ok\", 50, 4], \"passed\": true}, {\"check\": \"user reads supervisor csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"missing csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}], \"passed\": false}\n"},"broken":{"elapsed_ms":40.433,"exit_code":1,"observations":[{"actual":["ok",6144,9],"check":"machine writes machine csr","expected":["ok",6144,9],"passed":true},{"actual":"illegal","check":"user reads read-only counter","expected":["ok",2457,2457],"passed":false},{"actual":["ok",2457,2457],"check":"user set-bits with nonzero rs1 on read-only","expected":"illegal","passed":false},{"actual":"illegal","check":"supervisor touches machine csr","expected":"illegal","passed":true},{"actual":"illegal","check":"immediate write to read-only hart id","expected":"illegal","passed":true},{"actual":["ok",5,1],"check":"clear bits in user csr","expected":["ok",5,1],"passed":true},{"actual":["ok",5,7],"check":"set bits immediate form","expected":["ok",5,7],"passed":true},{"actual":["ok",7,4],"check":"custom machine read-write csr","expected":["ok",7,4],"passed":true},{"actual":["ok",50,4],"check":"machine counter is writable","expected":["ok",50,4],"passed":true},{"actual":"illegal","check":"user reads supervisor csr","expected":"illegal","passed":true},{"actual":"illegal","check":"missing csr","expected":"illegal","passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"machine writes machine csr\", \"actual\": [\"ok\", 6144, 9], \"expected\": [\"ok\", 6144, 9], \"passed\": true}, {\"check\": \"user reads read-only counter\", \"actual\": \"illegal\", \"expected\": [\"ok\", 2457, 2457], \"passed\": false}, {\"check\": \"user set-bits with nonzero rs1 on read-only\", \"actual\": [\"ok\", 2457, 2457], \"expected\": \"illegal\", \"passed\": false}, {\"check\": \"supervisor touches machine csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"immediate write to read-only hart id\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"clear bits in user csr\", \"actual\": [\"ok\", 5, 1], \"expected\": [\"ok\", 5, 1], \"passed\": true}, {\"check\": \"set bits immediate form\", \"actual\": [\"ok\", 5, 7], \"expected\": [\"ok\", 5, 7], \"passed\": true}, {\"check\": \"custom machine read-write csr\", \"actual\": [\"ok\", 7, 4], \"expected\": [\"ok\", 7, 4], \"passed\": true}, {\"check\": \"machine counter is writable\", \"actual\": [\"ok\", 50, 4], \"expected\": [\"ok\", 50, 4], \"passed\": true}, {\"check\": \"user reads supervisor csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"missing csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}], \"passed\": false}\n"},"fixed":{"elapsed_ms":40.346,"exit_code":0,"observations":[{"actual":["ok",6144,9],"check":"machine writes machine csr","expected":["ok",6144,9],"passed":true},{"actual":["ok",2457,2457],"check":"user reads read-only counter","expected":["ok",2457,2457],"passed":true},{"actual":"illegal","check":"user set-bits with nonzero rs1 on read-only","expected":"illegal","passed":true},{"actual":"illegal","check":"supervisor touches machine csr","expected":"illegal","passed":true},{"actual":"illegal","check":"immediate write to read-only hart id","expected":"illegal","passed":true},{"actual":["ok",5,1],"check":"clear bits in user csr","expected":["ok",5,1],"passed":true},{"actual":["ok",5,7],"check":"set bits immediate form","expected":["ok",5,7],"passed":true},{"actual":["ok",7,4],"check":"custom machine read-write csr","expected":["ok",7,4],"passed":true},{"actual":["ok",50,4],"check":"machine counter is writable","expected":["ok",50,4],"passed":true},{"actual":"illegal","check":"user reads supervisor csr","expected":"illegal","passed":true},{"actual":"illegal","check":"missing csr","expected":"illegal","passed":true}],"passed":true,"stderr":"","stdout":"{\"observations\": [{\"check\": \"machine writes machine csr\", \"actual\": [\"ok\", 6144, 9], \"expected\": [\"ok\", 6144, 9], \"passed\": true}, {\"check\": \"user reads read-only counter\", \"actual\": [\"ok\", 2457, 2457], \"expected\": [\"ok\", 2457, 2457], \"passed\": true}, {\"check\": \"user set-bits with nonzero rs1 on read-only\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"supervisor touches machine csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"immediate write to read-only hart id\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"clear bits in user csr\", \"actual\": [\"ok\", 5, 1], \"expected\": [\"ok\", 5, 1], \"passed\": true}, {\"check\": \"set bits immediate form\", \"actual\": [\"ok\", 5, 7], \"expected\": [\"ok\", 5, 7], \"passed\": true}, {\"check\": \"custom machine read-write csr\", \"actual\": [\"ok\", 7, 4], \"expected\": [\"ok\", 7, 4], \"passed\": true}, {\"check\": \"machine counter is writable\", \"actual\": [\"ok\", 50, 4], \"expected\": [\"ok\", 50, 4], \"passed\": true}, {\"check\": \"user reads supervisor csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}, {\"check\": \"missing csr\", \"actual\": \"illegal\", \"expected\": \"illegal\", \"passed\": true}], \"passed\": true}\n"}},"verified":true,"visibility":"public"}