{"abstract":"After writing x0, later instructions reading x0 see a nonzero value.","category":"Instruction set emulation","checks":8,"contract":"Input [prog]: [op, rd, a, b] with ops addi (x[a]+b), add, sub, lui (b<<12), slt (signed), sltu (unsigned), sltiu (x[a] < b sign-extended then taken unsigned), srai, srli, slli (shift amount b & 31). Registers x0..x31 start at 0 and hold unsigned 32-bit values; x0 always reads 0 and writes to it are discarded. Return sorted [index, value] of nonzero registers.","evaluation_group":"w2-instruction-set-emulation-rv-regfile-alu","failed_approach":"Excluding x1 as well drops legitimate writes to x1.","family":"w2-instruction-set-emulation-rv-regfile-alu-zero-register","id":"FA-89541","implementations":{"attempt":{"sha256":"6dfa229143b68ba1d9581e828ad77dd9305aaf64fc3a5ae4361e6d57a064f806","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    prog = args[0]\n    x = [0] * 32\n    M = 0xFFFFFFFF\n    def s(v):\n        return v - (1 << 32) if v >> 31 else v\n    for op, rd, a, b in prog:\n        if op == 'addi': r = x[a] + b\n        elif op == 'add': r = x[a] + x[b]\n        elif op == 'sub': r = x[a] - x[b]\n        elif op == 'lui': r = b << 12\n        elif op == 'slt': r = int(s(x[a]) < s(x[b]))\n        elif op == 'sltu': r = int(x[a] < x[b])\n        elif op == 'sltiu': r = int(x[a] < (b & M))\n        elif op == 'srai': r = s(x[a]) >> (b & 31)\n        elif op == 'srli': r = x[a] >> (b & 31)\n        else: r = x[a] << (b & 31)\n        if rd > 1:\n            x[rd] = r & M\n    return [[i, x[i]] for i in range(32) if x[i]]\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('writes to x0 are discarded', [[['addi', 0, 0, 6], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 8], ['add', 2, 1, 1]]], [[1, 8], [2, 16]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 3], ['add', 2, 1, 1]]], [[1, 1], [2, 2]]), ('negative results wrap', [[['addi', 1, 0, -2], ['sub', 2, 0, 1]]], [[1, 4294967294], [2, 2]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 2], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 2], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 6], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74566], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 6], [2, 1], [3, 1], [5, 305422336], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -32], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967264], [2, 4294967288], [3, 15], [4, 4294967280]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 33], ['slli', 3, 1, 31]]], [[1, 3], [2, 6], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 7], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 9], ['add', 2, 1, 1]]], [[1, 9], [2, 18]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 4], ['add', 2, 1, 1]]], [[1, 2], [2, 4]]), ('negative results wrap', [[['addi', 1, 0, -3], ['sub', 2, 0, 1]]], [[1, 4294967293], [2, 3]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 3], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 3], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 7], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74567], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 7], [2, 1], [3, 1], [5, 305426432], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -48], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967248], [2, 4294967284], [3, 15], [4, 4294967272]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 34], ['slli', 3, 1, 31]]], [[1, 3], [2, 12], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 8], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 10], ['add', 2, 1, 1]]], [[1, 10], [2, 20]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 5], ['add', 2, 1, 1]]], [[1, 3], [2, 6]]), ('negative results wrap', [[['addi', 1, 0, -4], ['sub', 2, 0, 1]]], [[1, 4294967292], [2, 4]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 4], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 4], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 8], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74568], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 8], [2, 1], [3, 1], [5, 305430528], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -64], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967232], [2, 4294967280], [3, 15], [4, 4294967264]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 35], ['slli', 3, 1, 31]]], [[1, 3], [2, 24], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 9], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 11], ['add', 2, 1, 1]]], [[1, 11], [2, 22]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 6], ['add', 2, 1, 1]]], [[1, 4], [2, 8]]), ('negative results wrap', [[['addi', 1, 0, -5], ['sub', 2, 0, 1]]], [[1, 4294967291], [2, 5]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 5], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 5], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 9], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74569], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 9], [2, 1], [3, 1], [5, 305434624], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -80], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967216], [2, 4294967276], [3, 15], [4, 4294967256]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 36], ['slli', 3, 1, 31]]], [[1, 3], [2, 48], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 10], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 12], ['add', 2, 1, 1]]], [[1, 12], [2, 24]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 7], ['add', 2, 1, 1]]], [[1, 5], [2, 10]]), ('negative results wrap', [[['addi', 1, 0, -6], ['sub', 2, 0, 1]]], [[1, 4294967290], [2, 6]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 6], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 6], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 10], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74570], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 10], [2, 1], [3, 1], [5, 305438720], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -96], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967200], [2, 4294967272], [3, 15], [4, 4294967248]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 37], ['slli', 3, 1, 31]]], [[1, 3], [2, 96], [3, 2147483648]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"broken":{"sha256":"69f1670e2e197fb5b68903ada6f62c3529931b6258f28c463d9863296dbdd37d","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    prog = args[0]\n    x = [0] * 32\n    M = 0xFFFFFFFF\n    def s(v):\n        return v - (1 << 32) if v >> 31 else v\n    for op, rd, a, b in prog:\n        if op == 'addi': r = x[a] + b\n        elif op == 'add': r = x[a] + x[b]\n        elif op == 'sub': r = x[a] - x[b]\n        elif op == 'lui': r = b << 12\n        elif op == 'slt': r = int(s(x[a]) < s(x[b]))\n        elif op == 'sltu': r = int(x[a] < x[b])\n        elif op == 'sltiu': r = int(x[a] < (b & M))\n        elif op == 'srai': r = s(x[a]) >> (b & 31)\n        elif op == 'srli': r = x[a] >> (b & 31)\n        else: r = x[a] << (b & 31)\n        if True:\n            x[rd] = r & M\n    return [[i, x[i]] for i in range(32) if x[i]]\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('writes to x0 are discarded', [[['addi', 0, 0, 6], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 8], ['add', 2, 1, 1]]], [[1, 8], [2, 16]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 3], ['add', 2, 1, 1]]], [[1, 1], [2, 2]]), ('negative results wrap', [[['addi', 1, 0, -2], ['sub', 2, 0, 1]]], [[1, 4294967294], [2, 2]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 2], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 2], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 6], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74566], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 6], [2, 1], [3, 1], [5, 305422336], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -32], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967264], [2, 4294967288], [3, 15], [4, 4294967280]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 33], ['slli', 3, 1, 31]]], [[1, 3], [2, 6], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 7], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 9], ['add', 2, 1, 1]]], [[1, 9], [2, 18]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 4], ['add', 2, 1, 1]]], [[1, 2], [2, 4]]), ('negative results wrap', [[['addi', 1, 0, -3], ['sub', 2, 0, 1]]], [[1, 4294967293], [2, 3]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 3], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 3], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 7], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74567], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 7], [2, 1], [3, 1], [5, 305426432], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -48], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967248], [2, 4294967284], [3, 15], [4, 4294967272]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 34], ['slli', 3, 1, 31]]], [[1, 3], [2, 12], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 8], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 10], ['add', 2, 1, 1]]], [[1, 10], [2, 20]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 5], ['add', 2, 1, 1]]], [[1, 3], [2, 6]]), ('negative results wrap', [[['addi', 1, 0, -4], ['sub', 2, 0, 1]]], [[1, 4294967292], [2, 4]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 4], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 4], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 8], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74568], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 8], [2, 1], [3, 1], [5, 305430528], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -64], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967232], [2, 4294967280], [3, 15], [4, 4294967264]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 35], ['slli', 3, 1, 31]]], [[1, 3], [2, 24], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 9], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 11], ['add', 2, 1, 1]]], [[1, 11], [2, 22]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 6], ['add', 2, 1, 1]]], [[1, 4], [2, 8]]), ('negative results wrap', [[['addi', 1, 0, -5], ['sub', 2, 0, 1]]], [[1, 4294967291], [2, 5]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 5], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 5], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 9], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74569], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 9], [2, 1], [3, 1], [5, 305434624], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -80], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967216], [2, 4294967276], [3, 15], [4, 4294967256]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 36], ['slli', 3, 1, 31]]], [[1, 3], [2, 48], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 10], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 12], ['add', 2, 1, 1]]], [[1, 12], [2, 24]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 7], ['add', 2, 1, 1]]], [[1, 5], [2, 10]]), ('negative results wrap', [[['addi', 1, 0, -6], ['sub', 2, 0, 1]]], [[1, 4294967290], [2, 6]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 6], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 6], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 10], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74570], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 10], [2, 1], [3, 1], [5, 305438720], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -96], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967200], [2, 4294967272], [3, 15], [4, 4294967248]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 37], ['slli', 3, 1, 31]]], [[1, 3], [2, 96], [3, 2147483648]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"fixed":{"sha256":"8e8e61801161c0895c00edd7c47a0463ff15f3c0035d94c0e370c2590fad2b27","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    prog = args[0]\n    x = [0] * 32\n    M = 0xFFFFFFFF\n    def s(v):\n        return v - (1 << 32) if v >> 31 else v\n    for op, rd, a, b in prog:\n        if op == 'addi': r = x[a] + b\n        elif op == 'add': r = x[a] + x[b]\n        elif op == 'sub': r = x[a] - x[b]\n        elif op == 'lui': r = b << 12\n        elif op == 'slt': r = int(s(x[a]) < s(x[b]))\n        elif op == 'sltu': r = int(x[a] < x[b])\n        elif op == 'sltiu': r = int(x[a] < (b & M))\n        elif op == 'srai': r = s(x[a]) >> (b & 31)\n        elif op == 'srli': r = x[a] >> (b & 31)\n        else: r = x[a] << (b & 31)\n        if rd != 0:\n            x[rd] = r & M\n    return [[i, x[i]] for i in range(32) if x[i]]\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('writes to x0 are discarded', [[['addi', 0, 0, 6], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 8], ['add', 2, 1, 1]]], [[1, 8], [2, 16]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 3], ['add', 2, 1, 1]]], [[1, 1], [2, 2]]), ('negative results wrap', [[['addi', 1, 0, -2], ['sub', 2, 0, 1]]], [[1, 4294967294], [2, 2]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 2], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 2], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 6], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74566], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 6], [2, 1], [3, 1], [5, 305422336], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -32], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967264], [2, 4294967288], [3, 15], [4, 4294967280]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 33], ['slli', 3, 1, 31]]], [[1, 3], [2, 6], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 7], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 9], ['add', 2, 1, 1]]], [[1, 9], [2, 18]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 4], ['add', 2, 1, 1]]], [[1, 2], [2, 4]]), ('negative results wrap', [[['addi', 1, 0, -3], ['sub', 2, 0, 1]]], [[1, 4294967293], [2, 3]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 3], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 3], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 7], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74567], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 7], [2, 1], [3, 1], [5, 305426432], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -48], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967248], [2, 4294967284], [3, 15], [4, 4294967272]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 34], ['slli', 3, 1, 31]]], [[1, 3], [2, 12], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 8], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 10], ['add', 2, 1, 1]]], [[1, 10], [2, 20]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 5], ['add', 2, 1, 1]]], [[1, 3], [2, 6]]), ('negative results wrap', [[['addi', 1, 0, -4], ['sub', 2, 0, 1]]], [[1, 4294967292], [2, 4]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 4], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 4], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 8], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74568], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 8], [2, 1], [3, 1], [5, 305430528], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -64], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967232], [2, 4294967280], [3, 15], [4, 4294967264]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 35], ['slli', 3, 1, 31]]], [[1, 3], [2, 24], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 9], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 11], ['add', 2, 1, 1]]], [[1, 11], [2, 22]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 6], ['add', 2, 1, 1]]], [[1, 4], [2, 8]]), ('negative results wrap', [[['addi', 1, 0, -5], ['sub', 2, 0, 1]]], [[1, 4294967291], [2, 5]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 5], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 5], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 9], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74569], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 9], [2, 1], [3, 1], [5, 305434624], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -80], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967216], [2, 4294967276], [3, 15], [4, 4294967256]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 36], ['slli', 3, 1, 31]]], [[1, 3], [2, 48], [3, 2147483648]])], [('writes to x0 are discarded', [[['addi', 0, 0, 10], ['add', 1, 0, 0], ['addi', 2, 0, 3]]], [[2, 3]]), ('x1 is an ordinary register', [[['addi', 1, 0, 12], ['add', 2, 1, 1]]], [[1, 12], [2, 24]]), ('32-bit wrap on add', [[['lui', 1, 0, 1048575], ['addi', 1, 1, 2047], ['addi', 1, 1, 2047], ['addi', 1, 1, 7], ['add', 2, 1, 1]]], [[1, 5], [2, 10]]), ('negative results wrap', [[['addi', 1, 0, -6], ['sub', 2, 0, 1]]], [[1, 4294967290], [2, 6]]), ('signed and unsigned compare', [[['addi', 1, 0, -1], ['addi', 2, 0, 6], ['slt', 3, 1, 2], ['sltu', 4, 1, 2], ['slt', 5, 2, 1]]], [[1, 4294967295], [2, 6], [3, 1]]), ('sltiu with negative immediate', [[['addi', 1, 0, 10], ['sltiu', 2, 1, -1], ['sltiu', 3, 0, 1], ['sltiu', 4, 1, 3], ['lui', 5, 0, 74570], ['sltiu', 6, 5, -1], ['sltiu', 7, 5, -2048]]], [[1, 10], [2, 1], [3, 1], [5, 305438720], [6, 1], [7, 1]]), ('arithmetic and logical right shift', [[['addi', 1, 0, -96], ['srai', 2, 1, 2], ['srli', 3, 1, 28], ['srai', 4, 1, 33]]], [[1, 4294967200], [2, 4294967272], [3, 15], [4, 4294967248]]), ('shift amount masked', [[['addi', 1, 0, 3], ['slli', 2, 1, 37], ['slli', 3, 1, 31]]], [[1, 3], [2, 96], [3, 2147483648]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"}},"limitations":"A deterministic bounded teaching model of one emulator rule; the instruction semantics are a stipulated contract inspired by common ISAs and are not a claim of cycle-exact or architectural conformance. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.","method":"Deterministic executable model with adversarial boundary fixtures.","provenance":{"created_by":"Failure Map","dependencies":"Python standard library","family":"w2-instruction-set-emulation-rv-regfile-alu-zero-register","generated_at":"2026-09-29T14:51:18.349302+00:00","license":"CC0-1.0","python":"3.12.14","seed":1,"split":"open-access"},"relevance":"Every RISC emulator implements a register file with a zero register and 32-bit wrapping arithmetic on a host with unbounded integers.","repair":"Skip writeback when rd is 0.","root_cause":"The writeback stage does not discard writes to register 0.","sha256":"340519e95cd5f6982a2748cd1fbe28d0e3308b83a18d419ebf69cd7500796355","title":"Writes to the zero register stick · case 01","variant":1,"variant_policy":"Five numbered records share a model and may reuse boundary fixtures.","verification":{"attempt":{"elapsed_ms":40.552,"exit_code":1,"observations":[{"actual":[[2,3]],"check":"writes to x0 are discarded","expected":[[2,3]],"passed":true},{"actual":[],"check":"x1 is an ordinary register","expected":[[1,8],[2,16]],"passed":false},{"actual":[],"check":"32-bit wrap on add","expected":[[1,1],[2,2]],"passed":false},{"actual":[],"check":"negative results wrap","expected":[[1,4294967294],[2,2]],"passed":false},{"actual":[[2,2],[3,1],[4,1]],"check":"signed and unsigned compare","expected":[[1,4294967295],[2,2],[3,1]],"passed":false},{"actual":[[2,1],[3,1],[4,1],[5,305422336],[6,1],[7,1]],"check":"sltiu with negative immediate","expected":[[1,6],[2,1],[3,1],[5,305422336],[6,1],[7,1]],"passed":false},{"actual":[],"check":"arithmetic and logical right shift","expected":[[1,4294967264],[2,4294967288],[3,15],[4,4294967280]],"passed":false},{"actual":[],"check":"shift amount masked","expected":[[1,3],[2,6],[3,2147483648]],"passed":false}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"writes to x0 are discarded\", \"actual\": [[2, 3]], \"expected\": [[2, 3]], \"passed\": true}, {\"check\": \"x1 is an ordinary register\", \"actual\": [], \"expected\": [[1, 8], [2, 16]], \"passed\": false}, {\"check\": \"32-bit wrap on add\", \"actual\": [], \"expected\": [[1, 1], [2, 2]], \"passed\": false}, {\"check\": \"negative results wrap\", \"actual\": [], \"expected\": [[1, 4294967294], [2, 2]], \"passed\": false}, {\"check\": \"signed and unsigned compare\", \"actual\": [[2, 2], [3, 1], [4, 1]], \"expected\": [[1, 4294967295], [2, 2], [3, 1]], \"passed\": false}, {\"check\": \"sltiu with negative immediate\", \"actual\": [[2, 1], [3, 1], [4, 1], [5, 305422336], [6, 1], [7, 1]], \"expected\": [[1, 6], [2, 1], [3, 1], [5, 305422336], [6, 1], [7, 1]], \"passed\": false}, {\"check\": \"arithmetic and logical right shift\", \"actual\": [], \"expected\": [[1, 4294967264], [2, 4294967288], [3, 15], [4, 4294967280]], \"passed\": false}, {\"check\": \"shift amount masked\", \"actual\": [], \"expected\": [[1, 3], [2, 6], [3, 2147483648]], \"passed\": false}], \"passed\": false}\n"},"broken":{"elapsed_ms":39.964,"exit_code":1,"observations":[{"actual":[[0,6],[1,12],[2,9]],"check":"writes to x0 are discarded","expected":[[2,3]],"passed":false},{"actual":[[1,8],[2,16]],"check":"x1 is an ordinary register","expected":[[1,8],[2,16]],"passed":true},{"actual":[[1,1],[2,2]],"check":"32-bit wrap on add","expected":[[1,1],[2,2]],"passed":true},{"actual":[[1,4294967294],[2,2]],"check":"negative results wrap","expected":[[1,4294967294],[2,2]],"passed":true},{"actual":[[1,4294967295],[2,2],[3,1]],"check":"signed and unsigned compare","expected":[[1,4294967295],[2,2],[3,1]],"passed":true},{"actual":[[1,6],[2,1],[3,1],[5,305422336],[6,1],[7,1]],"check":"sltiu with negative immediate","expected":[[1,6],[2,1],[3,1],[5,305422336],[6,1],[7,1]],"passed":true},{"actual":[[1,4294967264],[2,4294967288],[3,15],[4,4294967280]],"check":"arithmetic and logical right shift","expected":[[1,4294967264],[2,4294967288],[3,15],[4,4294967280]],"passed":true},{"actual":[[1,3],[2,6],[3,2147483648]],"check":"shift amount masked","expected":[[1,3],[2,6],[3,2147483648]],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"writes to x0 are discarded\", \"actual\": [[0, 6], [1, 12], [2, 9]], \"expected\": [[2, 3]], \"passed\": false}, {\"check\": \"x1 is an ordinary register\", \"actual\": [[1, 8], [2, 16]], \"expected\": [[1, 8], [2, 16]], \"passed\": true}, {\"check\": \"32-bit wrap on add\", \"actual\": [[1, 1], [2, 2]], \"expected\": [[1, 1], [2, 2]], \"passed\": true}, {\"check\": \"negative results wrap\", \"actual\": [[1, 4294967294], [2, 2]], \"expected\": [[1, 4294967294], [2, 2]], \"passed\": true}, {\"check\": \"signed and unsigned compare\", \"actual\": [[1, 4294967295], [2, 2], [3, 1]], \"expected\": [[1, 4294967295], [2, 2], [3, 1]], \"passed\": true}, {\"check\": \"sltiu with negative immediate\", \"actual\": [[1, 6], [2, 1], [3, 1], [5, 305422336], [6, 1], [7, 1]], \"expected\": [[1, 6], [2, 1], [3, 1], [5, 305422336], [6, 1], [7, 1]], \"passed\": true}, {\"check\": \"arithmetic and logical right shift\", \"actual\": [[1, 4294967264], [2, 4294967288], [3, 15], [4, 4294967280]], \"expected\": [[1, 4294967264], [2, 4294967288], [3, 15], [4, 4294967280]], \"passed\": true}, {\"check\": \"shift amount masked\", \"actual\": [[1, 3], [2, 6], [3, 2147483648]], \"expected\": [[1, 3], [2, 6], [3, 2147483648]], \"passed\": true}], \"passed\": false}\n"},"fixed":{"elapsed_ms":41.43,"exit_code":0,"observations":[{"actual":[[2,3]],"check":"writes to x0 are discarded","expected":[[2,3]],"passed":true},{"actual":[[1,8],[2,16]],"check":"x1 is an ordinary register","expected":[[1,8],[2,16]],"passed":true},{"actual":[[1,1],[2,2]],"check":"32-bit wrap on add","expected":[[1,1],[2,2]],"passed":true},{"actual":[[1,4294967294],[2,2]],"check":"negative results wrap","expected":[[1,4294967294],[2,2]],"passed":true},{"actual":[[1,4294967295],[2,2],[3,1]],"check":"signed and unsigned compare","expected":[[1,4294967295],[2,2],[3,1]],"passed":true},{"actual":[[1,6],[2,1],[3,1],[5,305422336],[6,1],[7,1]],"check":"sltiu with negative immediate","expected":[[1,6],[2,1],[3,1],[5,305422336],[6,1],[7,1]],"passed":true},{"actual":[[1,4294967264],[2,4294967288],[3,15],[4,4294967280]],"check":"arithmetic and logical right shift","expected":[[1,4294967264],[2,4294967288],[3,15],[4,4294967280]],"passed":true},{"actual":[[1,3],[2,6],[3,2147483648]],"check":"shift amount masked","expected":[[1,3],[2,6],[3,2147483648]],"passed":true}],"passed":true,"stderr":"","stdout":"{\"observations\": [{\"check\": \"writes to x0 are discarded\", \"actual\": [[2, 3]], \"expected\": [[2, 3]], \"passed\": true}, {\"check\": \"x1 is an ordinary register\", \"actual\": [[1, 8], [2, 16]], \"expected\": [[1, 8], [2, 16]], \"passed\": true}, {\"check\": \"32-bit wrap on add\", \"actual\": [[1, 1], [2, 2]], \"expected\": [[1, 1], [2, 2]], \"passed\": true}, {\"check\": \"negative results wrap\", \"actual\": [[1, 4294967294], [2, 2]], \"expected\": [[1, 4294967294], [2, 2]], \"passed\": true}, {\"check\": \"signed and unsigned compare\", \"actual\": [[1, 4294967295], [2, 2], [3, 1]], \"expected\": [[1, 4294967295], [2, 2], [3, 1]], \"passed\": true}, {\"check\": \"sltiu with negative immediate\", \"actual\": [[1, 6], [2, 1], [3, 1], [5, 305422336], [6, 1], [7, 1]], \"expected\": [[1, 6], [2, 1], [3, 1], [5, 305422336], [6, 1], [7, 1]], \"passed\": true}, {\"check\": \"arithmetic and logical right shift\", \"actual\": [[1, 4294967264], [2, 4294967288], [3, 15], [4, 4294967280]], \"expected\": [[1, 4294967264], [2, 4294967288], [3, 15], [4, 4294967280]], \"passed\": true}, {\"check\": \"shift amount masked\", \"actual\": [[1, 3], [2, 6], [3, 2147483648]], \"expected\": [[1, 3], [2, 6], [3, 2147483648]], \"passed\": true}], \"passed\": true}\n"}},"verified":true,"visibility":"public"}