{"abstract":"Writing with only the low-byte enable modifies the high byte.","category":"Digital logic simulation","checks":7,"contract":"Input [depth, mode, ops]; memory holds 16-bit words initialised to 0. Each op [we, addr, wdata, be, re]: be bit k enables byte lane k (bits 8k..8k+7). Addresses outside 0..depth-1 ignore writes and read 'x'. A read in the same cycle as a write returns the old word in mode 'read_first' and the merged new word in 'write_first'. re=0 yields None.","contract_signature":"*args","evaluation_group":"w2-digital-logic-simulation-sync-ram","failed_approach":"Handling the full-word case separately leaves single-lane writes swapped.","family":"w2-digital-logic-simulation-sync-ram-byte-lane-mask","id":"FA-89111","implementations":{"attempt":{"sha256":"178f88cd2456c00b1e8d41bbbc43a1bdd9d8ff7dbe1fbbb9ddac3d6038d3cc2c","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    depth, mode, ops = args\n    mem = [0] * depth\n    out = []\n    for we, addr, wdata, be, re in ops:\n        ok = 0 <= addr < depth\n        old = mem[addr] if ok else None\n        new = old\n        if we and ok:\n            for lane in range(2):\n                if be >> lane & 1:\n                    mask = 0xFFFF if be == 3 else 0xFF << (8 * (1 - lane))\n                    new = (new & ~mask) | (wdata & mask)\n            mem[addr] = new\n        if re:\n            if not ok:\n                out.append('x')\n            else:\n                out.append(new if mode == 'write_first' else old)\n        else:\n            out.append(None)\n    return out\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('full write then read-first read', [5, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [5, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [5, 'read_first', [[1, 3, 23041, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [5, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [5, 'read_first', [[1, -1, 30583, 3, 1], [0, 4, 0, 0, 1]]], ['x', 0]), ('out of range read', [5, 'read_first', [[0, 6, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [5, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 8738, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 8738])], [('full write then read-first read', [4, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [4, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [4, 'read_first', [[1, 3, 23042, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [4, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [4, 'read_first', [[1, -1, 30583, 3, 1], [0, 3, 0, 0, 1]]], ['x', 0]), ('out of range read', [4, 'read_first', [[0, 6, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [4, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 17476, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 17476])], [('full write then read-first read', [5, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [5, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [5, 'read_first', [[1, 3, 23043, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [5, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [5, 'read_first', [[1, -1, 30583, 3, 1], [0, 4, 0, 0, 1]]], ['x', 0]), ('out of range read', [5, 'read_first', [[0, 8, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [5, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 26214, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 26214])], [('full write then read-first read', [4, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [4, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [4, 'read_first', [[1, 3, 23044, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [4, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [4, 'read_first', [[1, -1, 30583, 3, 1], [0, 3, 0, 0, 1]]], ['x', 0]), ('out of range read', [4, 'read_first', [[0, 8, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [4, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 34952, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 34952])], [('full write then read-first read', [5, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [5, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [5, 'read_first', [[1, 3, 23045, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [5, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [5, 'read_first', [[1, -1, 30583, 3, 1], [0, 4, 0, 0, 1]]], ['x', 0]), ('out of range read', [5, 'read_first', [[0, 10, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [5, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 43690, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 43690])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"broken":{"sha256":"7a68376732243f7bebc04e5d2ac8f47ad033281943c2a5404e1dc58d7e788d0d","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    depth, mode, ops = args\n    mem = [0] * depth\n    out = []\n    for we, addr, wdata, be, re in ops:\n        ok = 0 <= addr < depth\n        old = mem[addr] if ok else None\n        new = old\n        if we and ok:\n            for lane in range(2):\n                if be >> lane & 1:\n                    mask = 0xFF << (8 * (1 - lane))\n                    new = (new & ~mask) | (wdata & mask)\n            mem[addr] = new\n        if re:\n            if not ok:\n                out.append('x')\n            else:\n                out.append(new if mode == 'write_first' else old)\n        else:\n            out.append(None)\n    return out\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('full write then read-first read', [5, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [5, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [5, 'read_first', [[1, 3, 23041, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [5, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [5, 'read_first', [[1, -1, 30583, 3, 1], [0, 4, 0, 0, 1]]], ['x', 0]), ('out of range read', [5, 'read_first', [[0, 6, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [5, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 8738, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 8738])], [('full write then read-first read', [4, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [4, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [4, 'read_first', [[1, 3, 23042, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [4, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [4, 'read_first', [[1, -1, 30583, 3, 1], [0, 3, 0, 0, 1]]], ['x', 0]), ('out of range read', [4, 'read_first', [[0, 6, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [4, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 17476, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 17476])], [('full write then read-first read', [5, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [5, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [5, 'read_first', [[1, 3, 23043, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [5, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [5, 'read_first', [[1, -1, 30583, 3, 1], [0, 4, 0, 0, 1]]], ['x', 0]), ('out of range read', [5, 'read_first', [[0, 8, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [5, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 26214, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 26214])], [('full write then read-first read', [4, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [4, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [4, 'read_first', [[1, 3, 23044, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [4, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [4, 'read_first', [[1, -1, 30583, 3, 1], [0, 3, 0, 0, 1]]], ['x', 0]), ('out of range read', [4, 'read_first', [[0, 8, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [4, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 34952, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 34952])], [('full write then read-first read', [5, 'read_first', [[1, 1, 43981, 3, 1], [0, 1, 0, 0, 1]]], [0, 43981]), ('write-first partial write', [5, 'write_first', [[1, 2, 4660, 3, 0], [1, 2, 65535, 1, 1], [0, 2, 0, 0, 1]]], [None, 4863, 4863]), ('high lane only', [5, 'read_first', [[1, 3, 23045, 2, 0], [0, 3, 0, 0, 1]]], [None, 23040]), ('address zero', [5, 'write_first', [[1, 0, 3855, 3, 1], [0, 0, 0, 0, 1]]], [3855, 3855]), ('negative address rejected', [5, 'read_first', [[1, -1, 30583, 3, 1], [0, 4, 0, 0, 1]]], ['x', 0]), ('out of range read', [5, 'read_first', [[0, 10, 0, 0, 1], [0, 1, 0, 0, 0]]], ['x', None]), ('read-first returns old data', [5, 'read_first', [[1, 1, 4369, 3, 0], [1, 1, 43690, 3, 1], [0, 1, 0, 0, 1]]], [None, 4369, 43690])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"}},"limitations":"A deterministic bounded teaching model of one simulator rule set; the contract is stipulated and is not a claim of conformance to any HDL standard or commercial simulator. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.","method":"Deterministic executable model with adversarial boundary fixtures.","provenance":{"created_by":"Failure Map","dependencies":"Python standard library","family":"w2-digital-logic-simulation-sync-ram-byte-lane-mask","generated_at":"2026-09-29T14:51:14.643397+00:00","license":"CC0-1.0","python":"3.12.14","seed":1,"split":"open-access"},"relevance":"RTL memory models must match the inferred RAM read-during-write and byte-enable behaviour or simulation diverges from silicon.","root_cause":"Enable bit k selects lane 1-k (big-endian lane numbering).","sha256":"cd99f7b6bf7d5f76e076187178e7487448a665404ae8d85b37594917d2fb89d2","title":"Byte enable bits mapped to the wrong lanes · case 01","variant":1,"variant_policy":"Five numbered records share a model and may reuse boundary fixtures.","verified":true,"visibility":"public","verification":{"attempt":{"elapsed_ms":41.816,"exit_code":1,"observations":[{"actual":[0,43981],"check":"full write then read-first read","expected":[0,43981],"passed":true},{"actual":[null,65332,65332],"check":"write-first partial write","expected":[null,4863,4863],"passed":false},{"actual":[null,1],"check":"high lane only","expected":[null,23040],"passed":false},{"actual":[3855,3855],"check":"address zero","expected":[3855,3855],"passed":true},{"actual":["x",0],"check":"negative address rejected","expected":["x",0],"passed":true},{"actual":["x",null],"check":"out of range read","expected":["x",null],"passed":true},{"actual":[null,4369,8738],"check":"read-first returns old data","expected":[null,4369,8738],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"full write then read-first read\", \"actual\": [0, 43981], \"expected\": [0, 43981], \"passed\": true}, {\"check\": \"write-first partial write\", \"actual\": [null, 65332, 65332], \"expected\": [null, 4863, 4863], \"passed\": false}, {\"check\": \"high lane only\", \"actual\": [null, 1], \"expected\": [null, 23040], \"passed\": false}, {\"check\": \"address zero\", \"actual\": [3855, 3855], \"expected\": [3855, 3855], \"passed\": true}, {\"check\": \"negative address rejected\", \"actual\": [\"x\", 0], \"expected\": [\"x\", 0], \"passed\": true}, {\"check\": \"out of range read\", \"actual\": [\"x\", null], \"expected\": [\"x\", null], \"passed\": true}, {\"check\": \"read-first returns old data\", \"actual\": [null, 4369, 8738], \"expected\": [null, 4369, 8738], \"passed\": true}], \"passed\": false}\n"},"broken":{"elapsed_ms":40.508,"exit_code":1,"observations":[{"actual":[0,43981],"check":"full write then read-first read","expected":[0,43981],"passed":true},{"actual":[null,65332,65332],"check":"write-first partial write","expected":[null,4863,4863],"passed":false},{"actual":[null,1],"check":"high lane only","expected":[null,23040],"passed":false},{"actual":[3855,3855],"check":"address zero","expected":[3855,3855],"passed":true},{"actual":["x",0],"check":"negative address rejected","expected":["x",0],"passed":true},{"actual":["x",null],"check":"out of range read","expected":["x",null],"passed":true},{"actual":[null,4369,8738],"check":"read-first returns old data","expected":[null,4369,8738],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"full write then read-first read\", \"actual\": [0, 43981], \"expected\": [0, 43981], \"passed\": true}, {\"check\": \"write-first partial write\", \"actual\": [null, 65332, 65332], \"expected\": [null, 4863, 4863], \"passed\": false}, {\"check\": \"high lane only\", \"actual\": [null, 1], \"expected\": [null, 23040], \"passed\": false}, {\"check\": \"address zero\", \"actual\": [3855, 3855], \"expected\": [3855, 3855], \"passed\": true}, {\"check\": \"negative address rejected\", \"actual\": [\"x\", 0], \"expected\": [\"x\", 0], \"passed\": true}, {\"check\": \"out of range read\", \"actual\": [\"x\", null], \"expected\": [\"x\", null], \"passed\": true}, {\"check\": \"read-first returns old data\", \"actual\": [null, 4369, 8738], \"expected\": [null, 4369, 8738], \"passed\": true}], \"passed\": false}\n"}},"member_only":{"stages":["fixed"],"fields":["implementations.fixed","verification.fixed","harness","repair"],"note":"The verified repair, its recorded checks, the repair description, and the scoring harness are available to members."}}