{"abstract":"A pulse narrower than the gate delay appears on the output instead of being swallowed.","category":"Digital logic simulation","checks":7,"contract":"Input [gate, rise_delay, fall_delay, v0, events]; gate is 'buf' or 'not', events are time-sorted [t, v] input changes. Output starts at f(v0) (not reported). Each input change schedules f(v) at t + rise_delay when f(v)==1 else t + fall_delay, and cancels every pending output event (inertial delay). Pending events maturing at or before the next input time are committed first. Report [time, value] only when the output value changes; all pending events are committed after the last input.","contract_signature":"*args","evaluation_group":"w2-digital-logic-simulation-inertial-delay-gate","failed_approach":"Keeping the most recent pending event still lets the leading edge of a narrow pulse through.","family":"w2-digital-logic-simulation-inertial-delay-gate-inertial-cancellation","id":"FA-88866","implementations":{"attempt":{"sha256":"149e79532757f4e918ff78e12c5bb6af44463541200470d25e5bba6dccde04f4","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    gate, dr, df, v0, events = args\n    f = (lambda v: 1 - v) if gate == 'not' else (lambda v: v)\n    out = f(v0)\n    q = []\n    res = []\n    for t, v in events + [[10 ** 9, None]]:\n        while q and q[0][0] <= t:\n            at, nv = q.pop(0)\n            if nv != out:\n                out = nv\n                res.append([at, nv])\n        if v is None:\n            break\n        q = q[-1:]\n        nv = f(v)\n        q.append([t + (dr if nv == 1 else df), nv])\n    return res\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('pulse shorter than inertial delay is filtered', ['buf', 4, 4, 0, [[10, 1], [12, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [21, 0]]], [[12, 1], [25, 0]]), ('inverter uses output polarity for delay', ['not', 2, 6, 0, [[10, 1], [30, 0]]], [[16, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [10, 0]]], [[12, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[1, 1]]], [[5, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [21, 0]]], [[25, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [41, 1]]], [[15, 1], [20, 0], [46, 1]])], [('pulse shorter than inertial delay is filtered', ['buf', 5, 5, 0, [[10, 1], [13, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [22, 0]]], [[12, 1], [26, 0]]), ('inverter uses output polarity for delay', ['not', 2, 7, 0, [[10, 1], [30, 0]]], [[17, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [11, 0]]], [[13, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[2, 1]]], [[6, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [22, 0]]], [[26, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [42, 1]]], [[15, 1], [20, 0], [47, 1]])], [('pulse shorter than inertial delay is filtered', ['buf', 6, 6, 0, [[10, 1], [14, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [23, 0]]], [[12, 1], [27, 0]]), ('inverter uses output polarity for delay', ['not', 2, 8, 0, [[10, 1], [30, 0]]], [[18, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [12, 0]]], [[14, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[3, 1]]], [[7, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [23, 0]]], [[27, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [43, 1]]], [[15, 1], [20, 0], [48, 1]])], [('pulse shorter than inertial delay is filtered', ['buf', 7, 7, 0, [[10, 1], [15, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [24, 0]]], [[12, 1], [28, 0]]), ('inverter uses output polarity for delay', ['not', 2, 9, 0, [[10, 1], [30, 0]]], [[19, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [13, 0]]], [[15, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[4, 1]]], [[8, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [24, 0]]], [[28, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [44, 1]]], [[15, 1], [20, 0], [49, 1]])], [('pulse shorter than inertial delay is filtered', ['buf', 8, 8, 0, [[10, 1], [16, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [25, 0]]], [[12, 1], [29, 0]]), ('inverter uses output polarity for delay', ['not', 2, 10, 0, [[10, 1], [30, 0]]], [[20, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [14, 0]]], [[16, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[5, 1]]], [[9, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [25, 0]]], [[29, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [45, 1]]], [[15, 1], [20, 0], [50, 1]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"},"broken":{"sha256":"37839b9161157203d69f38753ce669b7c0c17c01008a4e7b3f5ff7ab6084b968","source":"\"\"\"Failure Map reference implementation. Python standard library only.\"\"\"\nimport json\n\nN = 1\nobservations = []\ndef solve(*args):\n    gate, dr, df, v0, events = args\n    f = (lambda v: 1 - v) if gate == 'not' else (lambda v: v)\n    out = f(v0)\n    q = []\n    res = []\n    for t, v in events + [[10 ** 9, None]]:\n        while q and q[0][0] <= t:\n            at, nv = q.pop(0)\n            if nv != out:\n                out = nv\n                res.append([at, nv])\n        if v is None:\n            break\n        pass\n        nv = f(v)\n        q.append([t + (dr if nv == 1 else df), nv])\n    return res\ndef check(label, actual, expected):\n    observations.append({\"check\": label, \"actual\": actual, \"expected\": expected, \"passed\": actual == expected})\nfixtures = [[('pulse shorter than inertial delay is filtered', ['buf', 4, 4, 0, [[10, 1], [12, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [21, 0]]], [[12, 1], [25, 0]]), ('inverter uses output polarity for delay', ['not', 2, 6, 0, [[10, 1], [30, 0]]], [[16, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [10, 0]]], [[12, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[1, 1]]], [[5, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [21, 0]]], [[25, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [41, 1]]], [[15, 1], [20, 0], [46, 1]])], [('pulse shorter than inertial delay is filtered', ['buf', 5, 5, 0, [[10, 1], [13, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [22, 0]]], [[12, 1], [26, 0]]), ('inverter uses output polarity for delay', ['not', 2, 7, 0, [[10, 1], [30, 0]]], [[17, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [11, 0]]], [[13, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[2, 1]]], [[6, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [22, 0]]], [[26, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [42, 1]]], [[15, 1], [20, 0], [47, 1]])], [('pulse shorter than inertial delay is filtered', ['buf', 6, 6, 0, [[10, 1], [14, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [23, 0]]], [[12, 1], [27, 0]]), ('inverter uses output polarity for delay', ['not', 2, 8, 0, [[10, 1], [30, 0]]], [[18, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [12, 0]]], [[14, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[3, 1]]], [[7, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [23, 0]]], [[27, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [43, 1]]], [[15, 1], [20, 0], [48, 1]])], [('pulse shorter than inertial delay is filtered', ['buf', 7, 7, 0, [[10, 1], [15, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [24, 0]]], [[12, 1], [28, 0]]), ('inverter uses output polarity for delay', ['not', 2, 9, 0, [[10, 1], [30, 0]]], [[19, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [13, 0]]], [[15, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[4, 1]]], [[8, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [24, 0]]], [[28, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [44, 1]]], [[15, 1], [20, 0], [49, 1]])], [('pulse shorter than inertial delay is filtered', ['buf', 8, 8, 0, [[10, 1], [16, 0]]], []), ('wide pulse passes with rise and fall delays', ['buf', 2, 4, 0, [[10, 1], [25, 0]]], [[12, 1], [29, 0]]), ('inverter uses output polarity for delay', ['not', 2, 10, 0, [[10, 1], [30, 0]]], [[20, 0], [32, 1]]), ('redundant input event produces no output edge', ['buf', 1, 2, 1, [[5, 1], [14, 0]]], [[16, 0]]), ('final pending event is committed', ['buf', 4, 4, 0, [[5, 1]]], [[9, 1]]), ('inverter glitch cancelled', ['not', 4, 4, 1, [[10, 0], [12, 1], [25, 0]]], [[29, 1]]), ('output matures exactly at next input change', ['buf', 5, 5, 0, [[10, 1], [15, 0], [45, 1]]], [[15, 1], [20, 0], [50, 1]])]]\nfor label, args, expected in fixtures[N-1]:\n    check(label, solve(*args), expected)\nprint(json.dumps({\"observations\": observations, \"passed\": all(x[\"passed\"] for x in observations)}, ensure_ascii=False))\nraise SystemExit(0 if all(x[\"passed\"] for x in observations) else 1)\n"}},"limitations":"A deterministic bounded teaching model of one simulator rule set; the contract is stipulated and is not a claim of conformance to any HDL standard or commercial simulator. This reproducer isolates one failure mechanism. Results cover the supplied fixtures. Variants within a family share a test contract and should remain grouped when constructing evaluation splits. Related mechanisms with a shared evaluation_group must also remain together; these controlled models are not independent production incidents.","method":"Deterministic executable model with adversarial boundary fixtures.","provenance":{"created_by":"Failure Map","dependencies":"Python standard library","family":"w2-digital-logic-simulation-inertial-delay-gate-inertial-cancellation","generated_at":"2026-09-29T14:51:12.290848+00:00","license":"CC0-1.0","python":"3.12.14","seed":1,"split":"open-access"},"relevance":"Event-driven simulators filter pulses narrower than a gate delay; getting cancellation, polarity and flushing right determines the waveform.","root_cause":"Pending output events are never cancelled when a new input change arrives.","sha256":"8b29acbfa8c40130920312370c1cbc94a71fbb37aad25ebe804c5846ebc98c34","title":"Gate delay behaves as transport delay · case 01","variant":1,"variant_policy":"Five numbered records share a model and may reuse boundary fixtures.","verified":true,"visibility":"public","verification":{"attempt":{"elapsed_ms":41.883,"exit_code":1,"observations":[{"actual":[[14,1],[16,0]],"check":"pulse shorter than inertial delay is filtered","expected":[],"passed":false},{"actual":[[12,1],[25,0]],"check":"wide pulse passes with rise and fall delays","expected":[[12,1],[25,0]],"passed":true},{"actual":[[16,0],[32,1]],"check":"inverter uses output polarity for delay","expected":[[16,0],[32,1]],"passed":true},{"actual":[[12,0]],"check":"redundant input event produces no output edge","expected":[[12,0]],"passed":true},{"actual":[[5,1]],"check":"final pending event is committed","expected":[[5,1]],"passed":true},{"actual":[[14,1],[16,0],[25,1]],"check":"inverter glitch cancelled","expected":[[25,1]],"passed":false},{"actual":[[15,1],[20,0],[46,1]],"check":"output matures exactly at next input change","expected":[[15,1],[20,0],[46,1]],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"pulse shorter than inertial delay is filtered\", \"actual\": [[14, 1], [16, 0]], \"expected\": [], \"passed\": false}, {\"check\": \"wide pulse passes with rise and fall delays\", \"actual\": [[12, 1], [25, 0]], \"expected\": [[12, 1], [25, 0]], \"passed\": true}, {\"check\": \"inverter uses output polarity for delay\", \"actual\": [[16, 0], [32, 1]], \"expected\": [[16, 0], [32, 1]], \"passed\": true}, {\"check\": \"redundant input event produces no output edge\", \"actual\": [[12, 0]], \"expected\": [[12, 0]], \"passed\": true}, {\"check\": \"final pending event is committed\", \"actual\": [[5, 1]], \"expected\": [[5, 1]], \"passed\": true}, {\"check\": \"inverter glitch cancelled\", \"actual\": [[14, 1], [16, 0], [25, 1]], \"expected\": [[25, 1]], \"passed\": false}, {\"check\": \"output matures exactly at next input change\", \"actual\": [[15, 1], [20, 0], [46, 1]], \"expected\": [[15, 1], [20, 0], [46, 1]], \"passed\": true}], \"passed\": false}\n"},"broken":{"elapsed_ms":40.009,"exit_code":1,"observations":[{"actual":[[14,1],[16,0]],"check":"pulse shorter than inertial delay is filtered","expected":[],"passed":false},{"actual":[[12,1],[25,0]],"check":"wide pulse passes with rise and fall delays","expected":[[12,1],[25,0]],"passed":true},{"actual":[[16,0],[32,1]],"check":"inverter uses output polarity for delay","expected":[[16,0],[32,1]],"passed":true},{"actual":[[12,0]],"check":"redundant input event produces no output edge","expected":[[12,0]],"passed":true},{"actual":[[5,1]],"check":"final pending event is committed","expected":[[5,1]],"passed":true},{"actual":[[14,1],[16,0],[25,1]],"check":"inverter glitch cancelled","expected":[[25,1]],"passed":false},{"actual":[[15,1],[20,0],[46,1]],"check":"output matures exactly at next input change","expected":[[15,1],[20,0],[46,1]],"passed":true}],"passed":false,"stderr":"","stdout":"{\"observations\": [{\"check\": \"pulse shorter than inertial delay is filtered\", \"actual\": [[14, 1], [16, 0]], \"expected\": [], \"passed\": false}, {\"check\": \"wide pulse passes with rise and fall delays\", \"actual\": [[12, 1], [25, 0]], \"expected\": [[12, 1], [25, 0]], \"passed\": true}, {\"check\": \"inverter uses output polarity for delay\", \"actual\": [[16, 0], [32, 1]], \"expected\": [[16, 0], [32, 1]], \"passed\": true}, {\"check\": \"redundant input event produces no output edge\", \"actual\": [[12, 0]], \"expected\": [[12, 0]], \"passed\": true}, {\"check\": \"final pending event is committed\", \"actual\": [[5, 1]], \"expected\": [[5, 1]], \"passed\": true}, {\"check\": \"inverter glitch cancelled\", \"actual\": [[14, 1], [16, 0], [25, 1]], \"expected\": [[25, 1]], \"passed\": false}, {\"check\": \"output matures exactly at next input change\", \"actual\": [[15, 1], [20, 0], [46, 1]], \"expected\": [[15, 1], [20, 0], [46, 1]], \"passed\": true}], \"passed\": false}\n"}},"member_only":{"stages":["fixed"],"fields":["implementations.fixed","verification.fixed","harness","repair"],"note":"The verified repair, its recorded checks, the repair description, and the scoring harness are available to members."}}